Signal isolator having enhanced creepage characteristics

Patent metadata

Field	Value
Publication number	US-11289406-B2
Application number	US-201916574621-A
Country	US
Kind code	B2
Filing date	Sep 18, 2019
Priority date	Sep 18, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.

First claim

What is claimed is:

1. A leadless signal isolator IC package, comprising:
a leadframe having first and second die paddles each having opposed first and second surfaces;
a first die supported by the first surface of the first die paddle; and
a second die supported by the first surface of the second die paddle,
wherein the second surface of the first die paddle is exposed on exterior surface of the package, and wherein the second surface of the second die paddle is exposed on the exterior surface of the package,
wherein the IC package is rectangular having first, second, third and fourth sides, wherein the first and third sides are parallel to each other,
wherein the leadframe includes at least one tie bar exposed on the first side of the IC package,
wherein the second side of the IC package includes a series of package IO terminals such that at least one tie bar and the series of package IO terminals are located on adjacent sides of the IC package, and
wherein a first creepage distance comprises an edge of the at least one tie bar to an edge of a first one of the IO terminals of the IC package.

2. The leadless signal isolator IC package according to claim 1 , wherein the second surface of the first die paddle is aligned with the first die.

3. The leadless signal isolator IC package according to claim 2 , wherein a width of the second surface of the first die paddle is less than a width of the first die.

4. The leadless signal isolator IC package according to claim 3 , wherein the second surface of the second die paddle is aligned with the second die.

5. The leadless signal isolator IC package according to claim 4 , wherein a width of the second surface of the second die paddle is less than a width of the second die.

6. The leadless signal isolator IC package according to claim 5 , wherein the first and second die are formed from a single die.

7. The leadless signal isolator IC package according to claim 5 , wherein the first and second die are electrically isolated from each other.

8. A method of providing a leadless signal isolator IC package, comprising:
employing a leadframe having first and second die paddles each having opposed first and second surfaces;
employing a first die supported by the first surface of the first die paddle; and
employing a second die supported by the first surface of the second die paddle,
wherein the second surface of the first die paddle is exposed on exterior surface of the package, and wherein the second surface of the second die paddle is exposed on the exterior surface of the package,
wherein the IC package is rectangular having first, second, third and fourth sides, wherein the first and third sides are parallel to each other,
wherein the leadframe includes at least one tie bar exposed on the first side of the IC package,
wherein the second side of the IC package includes a series of package IO terminals such that at least one tie bar and the series of package IO terminals are located on adjacent sides of the IC package, and
wherein a first creepage distance comprises an edge of the at least one tie bar to an edge of a first one of the IO terminals of the IC package.

9. The method according to claim 8 , wherein the second surface of the first die paddle is aligned with the first die.

10. The method according to claim 9 , wherein a width of the second surface of the first die paddle is less than a width of the first die.

11. The method according to claim 10 , wherein the second surface of the second die paddle is aligned with the second die.

12. The method according to claim 11 , wherein a width of the second surface of the second die paddle is less than a width of the second die.

13. The method according to claim 12 , wherein the first and second die are formed from a single die.

14. The method package according to claim 13 , wherein the first and second die are electrically isolated from each other.

Assignees

• Allegro Microsystems Llc

Inventors

• Briano Robert A
• Liu Shixi Louis
• Taylor William P

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W72/551

  Materials of bond wires · CPC title