Power MOSFET and JBSFET cell topologies with superior high frequency figure of merit

Patent metadata

Field	Value
Publication number	US-11276779-B1
Application number	US-202017014368-A
Country	US
Kind code	B1
Filing date	Sep 8, 2020
Priority date	Mar 20, 2017
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A vertical insulated-gate field effect transistor includes a semiconductor substrate and a gate electrode on a first surface thereof. This gate electrode has a plurality of eight (or more) sided openings extending therethrough. Each of these openings has eight (or more) sidewalls, including a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening. A source electrode is also provided, which extends into the openings. This source electrode may ohmically contact a source region within the semiconductor substrate. If the field effect transistor is a JBSFET, the source electrode may also form a Schottky rectifying junction with a drift region within the semiconductor substrate.

First claim

That which is claimed is:

1. A vertical insulated-gate field effect transistor, comprising:
a semiconductor substrate;
a gate electrode on a first surface of said semiconductor substrate, said gate electrode having an at least eight-sided opening extending therethrough, which defines at least eight sidewalls thereof, said at least eight sidewalls comprising a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening; and
a source electrode extending into the opening in said gate electrode.

2. The transistor of claim 1 , wherein said semiconductor substrate comprises a base region therein extending opposite said gate electrode; and wherein said source electrode is electrically connected to the base region.

3. The transistor of claim 1 , further comprising a drain electrode on a second surface of said semiconductor substrate, which extends opposite the first surface.

4. The transistor of claim 1 , wherein all of the at least eight sidewalls are flat relative to the center of the opening.

5. The transistor of claim 4 , wherein the at least eight-sided opening is in the shape of an octagon.

6. The transistor of claim 1 , wherein said gate electrode comprises a quad-arrangement of four generally octagon-shaped gate electrode regions electrically coupled together by four generally rectangular-shaped gate electrode regions.

7. The transistor of claim 6 , wherein the at least eight-sided opening is in the shape of an octagon.

8. The transistor of claim 6 , wherein the at least eight-sided opening includes four flat sidewalls having a first length and four flat sidewalls having a second length unequal to the first length.

9. The transistor of claim 1 , wherein the insulated-gate field effect transistor is a JBSFET.

10. The transistor of claim 9 , wherein the JBSFET comprises a Schottky rectifying contact within the at least eight-sided opening.

11. A vertical insulated-gate field effect transistor, comprising:
a semiconductor substrate;
a gate electrode on a first surface of said semiconductor substrate, said gate electrode having an at least eight-sided opening extending therethrough, which defines at least eight sidewalls thereof that are flat or concave relative to a center of the opening; and
a source electrode extending into the opening in said gate electrode.

12. The transistor of claim 11 , wherein the at least eight sidewalls includes a plurality of arcuate-shaped sidewalls, which are concave relative to the center of the opening.

13. The transistor of claim 12 , wherein centers of the plurality of arcuate-shaped sidewalls are spaced-apart from the center of the opening.

14. The transistor of claim 12 , wherein the at least eight sidewalls includes a plurality of flat sidewalls.

15. The transistor of claim 11 , wherein the at least eight sidewalls have equivalent lengths.

16. The transistor of claim 11 , wherein the at least eight-sided opening is an octagonal-shaped opening.

17. The transistor of claim 16 , wherein the insulated-gate field effect transistor is a JBSFET having a four-sided Schottky rectifying contact within the octagonal-shaped opening.

18. The transistor of claim 11 , wherein the insulated-gate field effect transistor is a JBSFET having a Schottky rectifying contact within the at least eight-sided opening.

19. The transistor of claim 11 , wherein said semiconductor substrate comprises a source region of first conductivity type extending adjacent the first surface thereof; and wherein a portion of said source electrode in the opening forms an ohmic contact with the source region.

20. The transistor of claim 19 , wherein said semiconductor substrate comprises a base region of second conductivity type therein, which extends opposite said gate electrode and forms a P—N rectifying junction with the source region; and wherein said source electrode is electrically connected to the base region.

21. The transistor of claim 11 , further comprising a drain electrode on a second surface of said semiconductor substrate, which extends opposite the first surface.

22. A silicon carbide power device, comprising:
a semiconductor substrate;
a two-dimensional (2D) array of vertical insulated-gate field effect transistor unit cells (IGFETs) in said semiconductor substrate, said 2D array of IGFETs having a contiguous gate electrode that spans the IGFETs therein, with each of said IGFETs having: (i) a lateral rectangular dimension of L×W, and (ii) a corresponding at least eight-sided opening extending through the contiguous gate electrode, where L is a length of an IGFET and W is a width of an IGFET as measured along a surface of said semiconductor substrate, and where each sidewall of each at least eight-sided opening is flat or concave relative to a center of its corresponding opening; and
a source electrode extending into the openings in the contiguous gate electrode.

23. The power device of claim 22 , wherein an area (A) of each of the openings in the contiguous gate electrodes is equivalent to: 0.1(L×W)≤A≤0.3(L×W).

24. The power device of claim 23 , wherein the IGFETs are configured as JBSFETs; and wherein an area (A) of each of the openings in the contiguous gate electrodes is equivalent to: 0.1(L×W)≤A≤0.3(L×W).

25. A monolithically-integrated AC switch, comprising:
a semiconductor substrate having first and second insulated-gate field effect transistors therein, which comprise:
first and second spaced-apart and independently-controllable source terminals extending adjacent a first surface of said semiconductor substrate;
a common drain electrode extending adjacent a second surface of said semiconductor substrate; and
first and second gate electrodes on the first surface of said semiconductor substrate, said first gate electrode having an at least eight-sided first opening extending therethrough, which receives a portion of said first source terminal therein, said at least eight-sided first opening defined by at least eight sidewalls that are flat or concave relative to a center of the first opening.

26. The AC switch of claim 25 , wherein said second gate electrode has an at least eight-sided second opening extending therethrough, which receives a portion of said second source terminal therein; and wherein the second opening in said second gate electrode is defined by at least eight sidewalls that are flat or concave relative to a center of the second opening.

Assignees

• Univ North Carolina State

Inventors

• Baliga Bantval Jayant

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title