Systems and methods for fabricating cross-pillar superjunction structures for semiconductor power conversion devices
US-2024038836-A1 · Feb 1, 2024 · US
US9947741B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9947741-B2 |
| Application number | US-201715424533-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 3, 2017 |
| Priority date | Jul 18, 2013 |
| Publication date | Apr 17, 2018 |
| Grant date | Apr 17, 2018 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.
Opening claim text (preview).
What is claimed is: 1. A field-effect semiconductor device, comprising: a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the edge; a source metallization arranged on the first surface; and a drain metallization, in a vertical cross-section substantially orthogonal to the first surface, the semiconductor body further comprising: a plurality of alternating drift portions and compensation regions arranged in the active area, the drift portions being of a first conductivity type and in Ohmic contact with the drain metallization, the compensation regions being of a second conductivity type and in Ohmic contact with the source metallization, and an integrated dopant concentration of the drift portions substantially matching an integrated dopant concentration of the compensation regions; a low-doped semiconductor region of the first conductivity type arranged in the peripheral area and having a second maximum doping concentration lower than a first maximum doping concentration of the drift portions; at least one pillar region of the second conductivity type in Ohmic contact with the source metallization, arranged in the peripheral area and between the low-doped semiconductor region and the drift portions, and having an integrated dopant concentration smaller than the integrated dopant concentration of the compensation regions divided by a number of the compensation regions; and at least one pillar region of the first conductivity type arranged between the at least one pillar region of the second conductivity type and the compensation regions, and having an integrated dopant concentration smaller than the integrated dopant concentration of the drift portions divided by a number of the drift portions, wherein the integrated dopant concentration of the at least one pillar region of the second conductivity type is smaller than the integrated dopant concentration of the at least one pillar region of the first conductivity type. 2. The field-effect semiconductor device of claim 1 , further comprising at least one of: a first semiconductor region of the first conductivity type adjoining the drift portions and compensation regions, a first edge termination region of the second conductivity type adjoining the low-doped semiconductor region; and a further semiconductor region of the first conductivity type comprising a third maximum doping concentration higher than the second maximum doping concentration, being in Ohmic contact with the low-doped semiconductor region, and being arranged between the edge and the first edge termination region. 3. The field-effect semiconductor device of claim 2 , wherein the semiconductor body further comprises in the peripheral area a second edge termination region of the first conductivity type comprising a fourth maximum doping concentration higher than the second maximum doping concentration, the second edge termination region being in electric connection with the drain metallization, adjoining the first edge termination region, and being arranged between the first edge termination region and the first surface. 4. The field-effect semiconductor device of claim 3 , wherein the second edge termination region comprises a first portion and a second portion that has a higher maximum doping concentration than the first portion and is arranged between the first portion and the edge. 5. The field-effect semiconductor device of claim 1 , further comprising in the peripheral area at least one of: a first field plate arranged on the first surface and in electric connection with the drain metallization; and a second field plate arranged on the first surface and in electric connection with the source metallization or with a gate metallization arranged on the first surface and spaced apart from the source metallization. 6. The field-effect semiconductor device of claim 5 , wherein the first edge termination region comprises a first portion and a second portion that has a lower integrated doping concentration than the first portion and is arranged between the first portion and the edge, and/or wherein an interface between the first portion and the second portion is, in a projection onto the surface, arranged between the first field plate and the second field plate. 7. The field-effect semiconductor device of claim 5 , wherein the first field plate is, in a normal projection onto the first surface, arranged between the edge and an outermost of the alternating pillar regions of the first conductivity type and pillar regions of the second conductivity type. 8. The field-effect semiconductor device of claim 1 , wherein the active area is surrounded by the at least one pillar region of the second conductivity type when viewed from above. 9. The field-effect semiconductor device of claim 1 , wherein the maximum doping concentration of the low-doped semiconductor region is lower than a maximum doping concentration of the at least one pillar region of the first conductivity type. 10. A field-effect semiconductor device, comprising: a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the edge; a source metallization arranged on the first surface; and a drain metallization, in a vertical cross-section substantially orthogonal to the first surface, the semiconductor body further comprising: a plurality of alternating drift portions and compensation regions arranged in the active area, the drift portions being of a first conductivity type and in Ohmic contact with the drain metallization, the compensation regions being of a second conductivity type and in Ohmic contact with the source metallization, and an integrated dopant concentration of the drift portions substantially matching an integrated dopant concentration of the compensation regions; a low-doped semiconductor region of the first conductivity type arranged in the peripheral area and a having maximum doping concentration lower than a maximum doping concentration of the drift portions; at least one further compensation region of the second conductivity type in Ohmic contact with the source metallization, arranged in the peripheral area and between the low-doped semiconductor region and the drift portions, and having an integrated dopant concentration smaller than the integrated dopant concentration of the compensation regions of the active area divided by a number of the compensation regions of the active area; at least one semiconductor region of the first conductivity type arranged between the at least one further compensation region and the compensation regions of the active area, and having an integrated dopant concentration in a range from about 50% to about 99% of the integrated dopant concentration of the drift portions divided by the number of the drift portions. 11. The field-effect semiconductor device of claim 10 , wherein the drift portions and the compensation regions are substantially stripe shaped when viewed from above. 12. A field-effect semiconductor device, comprising: a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the edge; a source metallization arranged on the first surface; and a drain metallization, in a vertical cross-section substantially orthogonal to the firs
by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title
Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.