Bonding pads including interfacial electromigration barrier layers and methods of making the same

Patent metadata

Field	Value
Publication number	US-11270963-B2
Application number	US-202016742213-A
Country	US
Kind code	B2
Filing date	Jan 14, 2020
Priority date	Jan 14, 2020
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.

First claim

What is claimed is:

1. A structure comprising a first semiconductor die, wherein the first semiconductor die comprises:
a first pad-level dielectric layer embedding first bonding pads and located over a first substrate, wherein each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer and comprises:
a first metallic liner comprising a first metallic liner material and contacting a sidewall of the respective pad cavity;
a first metallic fill material portion embedded in the first metallic liner; and
a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner, wherein peripheral grooves are located over the metallic electromigration barrier material in a peripheral portion of each of the first bonding pads.

2. The structure of claim 1 , wherein a combination of the first metallic liner and the metallic electromigration barrier layer encapsulates the first metallic fill material portion.

3. The structure of claim 1 , wherein a distal surface of the first pad-level dielectric layer is located within a same horizontal plane as a distal surface of the metallic electromigration barrier layer.

4. The structure of claim 1 , wherein:
the first metallic liner comprises an inner sidewall;
a distal region of the inner sidewall contacts the metallic electromigration barrier layer at a first interface; and
a proximal region of the inner sidewall contacts the first metallic fill material portion at a second interface located within a same two-dimensional plane as the first interface.

5. The structure of claim 1 , wherein the second interface is vertically offset from a horizontal plane including a distal horizontal surface of the metallic electromigration barrier layer by a vertical spacing that is greater than a thickness of the metallic electromigration barrier layer.

6. The structure of claim 1 , wherein a contact area between the first metallic liner and the metallic electromigration barrier layer has an upper edge located within a horizontal plane including a distal surface of the first pad-level dielectric layer.

7. The structure of claim 6 , wherein a peripheral region of the first metallic fill material portion is vertically recessed from the horizontal plane including the distal surface of the first pad-level dielectric layer by a vertical recess distance that is greater than a thickness of the metallic electromigration barrier layer.

8. The structure of claim 1 , wherein:
the first metallic liner material comprises a metallic nitride material;
the first metallic fill material portion comprises copper or a copper alloy; and
the metallic electromigration barrier layer comprises at least one material selected from TaN, TiN, WN, Ta, Ti, W, Ru, or alloys thereof.

9. The structure of claim 1 , the metallic electromigration barrier layer is laterally spaced from the first pad-level dielectric layer by the first metallic liner.

10. The structure of claim 1 , further comprising a second semiconductor die comprising second bonding pads that are bonded to a respective one of the first bonding pads.

11. The structure of claim 10 , wherein each of the second bonding pads comprises:
a second metallic liner comprising a second metallic liner material; and
a second metallic fill material portion contacting the second metallic liner and a respective one of the metallic electromigration barrier layers.

12. The structure of claim 11 , wherein:
the second metallic liner material comprises a metallic nitride material;
the second metallic fill material portion comprises copper or a copper alloy; and
an entirety of distal surfaces of a metallic electromigration barrier layer and a first metallic liner within each of the first bonding pads is in contact with a horizontal surface of one of the second metallic fill material portions.

13. The structure of claim 10 , wherein:
one of the first and second semiconductor dies further comprises a memory die containing a three-dimensional memory device; and
another one of the first and second semiconductor dies further comprises a control circuit configured to control operation of the three-dimensional memory device.

14. The structure of claim 1 , wherein the peripheral grooves are not filled with any solid phase material.

15. The structure of claim 1 , wherein:
the first metallic fill material portion has a top surface containing a first horizontally-extending surface segment in a first horizontal plane;
the metallic electromigration barrier layer has a top surface containing a second horizontally-extending surface segment in a second horizontal plane located below the first horizontal plane; and
the peripheral grooves extend downward from the first horizontal plane below the second horizontal plane.

16. The structure of claim 15 , wherein the top surface of the metallic electromigration barrier layer within each of the first bonding pads further comprises:
a first vertically-extending surface segment that defines an outer boundary of the peripheral groove; and
a second vertically-extending surface segment that is adjoined to an edge of the first horizontally-extending surface segment and defines an inner boundary of the peripheral groove.

17. The structure of claim 1 , wherein each of the peripheral grooves have a configuration of a moat that continuously laterally extends around and laterally surrounds a topmost portion of the first metallic fill material portion within each of the first bonding pads.

18. The structure of claim 10 , wherein each of the second bonding pads comprises a bottom surface that includes an additional peripheral groove that extends upward from a horizontal plane including a horizontally-extending surface segment of the bottom surface, wherein the additional peripheral groove is not filled with any solid phase material.

19. The structure of claim 18 , wherein an inner periphery of the additional peripheral groove laterally encloses and is located entirely outside of an outer periphery of a respective peripheral groove of the first bonding pads for at least one of the second bonding pads.

20. The structure of claim 18 , wherein an entirety of a horizontally-extending surface segment of the top surface of each of the first bonding pads contacts the horizontally-extending surface segment of the bottom surface of a respective one of the second bonding pads.

Assignees

• Sandisk Technologies Llc

Inventors

• Wu Chen
• Rabkin Peter
• Higashitani Masaaki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title