Superconducting bump bonds

Patent metadata

Field	Value
Publication number	US-2018366634-A1
Application number	US-201516062064-A
Country	US
Kind code	A1
Filing date	Dec 30, 2015
Priority date	Dec 15, 2015
Publication date	Dec 20, 2018
Grant date	—

Abstract

A device ( 100 ) includes a first chip ( 104 ) having a first circuit element ( 112 ), a first interconnect pad ( 116 ) in electrical contact ( 118 ) with the first circuit element, and a barrier layer ( 120 ) on the first interconnect pad, a superconducting bump bond ( 106 ) on the barrier layer, and a second chip ( 102 ) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element ( 108 ), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

First claim

What is claimed is:

1 . A device comprising:
a first chip comprising a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad; a superconducting bump bond on the barrier layer; and a second chip joined to the first chip by the superconducting bump bond, the second chip comprising a first quantum circuit element, wherein the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.

2 . The device of claim 1 , wherein the first interconnect pad is aluminum.

3 . The device of claim 1 , wherein the barrier layer is titanium nitride.

4 . The device of claim 1 , wherein the superconducting bump bond is indium.

5 . The device of claim 1 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device.

6 . The device of claim 1 , wherein the first circuit element comprises a second quantum circuit element.

7 . The device of claim 1 , wherein at least one of the first chip and the second chip comprises a silicon substrate.

8 . The device of claim 1 , wherein at least one of the first chip and the second chip comprises a sapphire substrate.

9 . The device of claim 1 , wherein a first surface of the first chip is spaced apart from and faces a first surface of the second chip to form a gap.

10 . A method comprising:
providing a first chip comprising a first circuit element; forming a first aluminum interconnect pad on a first surface of the first chip so that the first aluminum interconnect pad is electrically connected to the first circuit element; forming a first titanium nitride barrier layer on the first aluminum interconnect pad; providing a second chip comprising a second circuit element; forming an indium bump bond; and joining the first chip to the second chip with the indium bump bond so that the first circuit element is electrically connected to the second circuit element, wherein joining the first chip to the second chip is performed at room temperature.

11 . The method of claim 10 , wherein room temperature is between approximately 18° C. and approximately 30° C.

12 . The method of claim 11 , further comprising removing a native oxide from the first aluminum interconnect pad prior to forming the first titanium nitride barrier layer.

13 . The method of claim 12 , wherein removing the native oxide comprises ion milling a surface of the first aluminum interconnect pad.

14 . The method of claim 11 , wherein forming the first titanium nitride barrier comprises reactive sputtering titanium nitride on the first aluminum interconnect pad.

15 . The method of claim 11 , further comprising ion milling a surface of the first titanium nitride barrier layer prior to joining the first chip to the second chip.

16 . The method of claim 11 , further comprising exposing a surface of the indium bump bond to a H 2 plasma.

17 . The method of claim 11 , further comprising:
forming a second aluminum interconnect pad on a first surface of the second chip so that the second aluminum interconnect pad is electrically connected to the second circuit element; and forming a second titanium nitride barrier layer on the second aluminum interconnect pad of the second chip.

18 . The method of claim 17 , further comprising removing a native oxide from the second aluminum interconnect pad of the second chip prior to forming the second titanium nitride barrier layer.

19 . The method of claim 18 , wherein removing the native oxide from the second aluminum interconnect pad comprises ion milling a surface of the second aluminum interconnect pad.

20 . The method of claim 17 , wherein forming the second titanium nitride barrier layer on the second aluminum interconnect pad comprises reactive sputtering titanium nitride on the second aluminum interconnect pad.

21 . The method of claim 17 , further comprising ion milling a surface of the second titanium nitride barrier layer prior to joining the first chip to the second chip.

22 . The method of claim 17 , wherein forming the indium bump bond comprises depositing indium on the first titanium nitride barrier, on the second titanium nitride barrier, or on both the first and second titanium nitride barriers.

23 . The method of claim 11 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device and the second circuit element comprises a quantum circuit element.

24 . The method of claim 11 , wherein the first circuit element comprises first quantum circuit element and the second circuit element comprises a second quantum circuit element.

25 . A method comprising:
transferring data between a first chip and a second chip through a superconducting bump bond that joins the first chip to the second chip, wherein the first chip comprises a first quantum circuit element and the second chip comprises a first circuit element.

26 . The method of claim 25 , further comprising:
operating the first quantum circuit element to produce the data, wherein transferring the data comprises transferring the data from the first quantum circuit element of the first chip to the first circuit element of the second chip.

27 . The method of claim 26 , wherein the first circuit element comprises a second quantum circuit element or a classical circuit element.

28 . The method of claim 25 , further comprising:
operating the first circuit element to produce the data, wherein transferring the data comprises transferring the data from the first circuit element of the second chip to the first quantum circuit element of the first chip.

29 . The method of claim 28 , wherein the first circuit element comprises a second quantum circuit element or a classical circuit element.

Assignees

• Mutus Joshua Yousouf
• Lucero Anthony Erik
• Google Llc

Inventors

• Mutus Joshua Yousouf
• Lucero Erik Anthony

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07232

  Compression bonding, e.g. thermocompression bonding · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title