Method for forming a via hole self-aligned with a metal block on a substrate

Patent metadata

Field	Value
Publication number	US-11270912-B2
Application number	US-202017110631-A
Country	US
Kind code	B2
Filing date	Dec 3, 2020
Priority date	Dec 12, 2019
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

First claim

What is claimed is:

1. A method for forming a via hole self-aligned with a metal block on a substrate, the substrate comprising an interlayer dielectric layer, the method comprising:
forming a metallic layer on the interlayer dielectric layer;
forming a dielectric layer on the metallic layer;
forming a plurality of parallel spacer line structures on the dielectric layer, wherein the parallel spacer line structures extend along an upper surface of the dielectric layer;
forming a sidewall oxide layer on respective sidewalls of the plurality of parallel spacer line structures such that a portion of the dielectric layer is exposed between adjacent sidewall oxide layers of the parallel spacer line structures;
forming a first sacrificial layer covering exposed portions of the dielectric layer and enclosing the parallel spacer line structures;
forming an opening in the first sacrificial layer to expose a first portion of the dielectric layer between adjacent sidewall oxide layers of the parallel spacer line structures;
etching, via the opening in the first sacrificial layer, through the first portion of the dielectric layer, thereby forming an opening in the dielectric layer and exposing a first portion of the metallic layer;
removing the first sacrificial layer;
forming a second sacrificial layer that covers the dielectric layer and the first portion of the metallic layer and encloses the parallel spacer line structures;
forming an opening in the second sacrificial layer, wherein the opening in the second sacrificial layer partially overlaps the opening in the dielectric layer and exposes a second portion of the metallic layer, and wherein the second portion of the metallic layer corresponds to a portion of the first portion of the metallic layer;
selectively depositing a metal block on the exposed second portion of the metallic layer;
removing the second sacrificial layer, thereby exposing a remaining portion of the first portion of the metallic layer in the opening in the dielectric layer; and
etching, via the opening in the dielectric layer, through the remaining portion of the first portion of the metallic layer and the interlayer dielectric layer, thereby forming a via hole self-aligned with the metal block.

2. The method according to claim 1 , wherein the metallic layer comprises TiN, Ru, AlON, AlN, Pt, or TiO 2 .

3. The method according to claim 1 , wherein the metal block comprises Ru, Rh, Pd, Os, Ir, or Pt.

4. The method according to claim 1 , wherein the selective deposition of the metal block is performed by area selective deposition (ASD).

5. The method according to claim 4 , wherein the selective deposition of the metal block is performed by atomic layer deposition (ALD).

6. The method according to claim 1 , wherein a lateral dimension of the opening in the first sacrificial layer in a direction along the parallel spacer line structures is 1 to 2 times a width of the via hole.

7. The method according to claim 1 , wherein a lateral dimension of the opening in the first sacrificial layer in a direction transverse to the parallel spacer line structures is 1.5 to 5 times a width of the via hole.

8. The method according to claim 1 , wherein the dielectric layer comprises SiN, SiO 2 , or SiCN.

9. The method according to claim 1 , wherein the parallel spacer line structures comprise amorphous silicon, a-Si, amorphous carbon, a-C, or SiO 2 .

10. The method according to claim 1 , wherein the sidewall oxide layers comprise SiO 2 , SiN, or TiO x .

11. The method according to claim 1 , wherein the interlayer dielectric layer comprises SiO 2 or SiCOH.

Assignees

• Imec Vzw

Inventors

• O'Toole Martin
• Wilson Christopher
• Tokei Zsolt
• Kim Ryan Ryoung Han

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title