Self-alignment of metal and via using selective deposition

Patent metadata

Field	Value
Publication number	US-9837314-B2
Application number	US-201715423320-A
Country	US
Kind code	B2
Filing date	Feb 2, 2017
Priority date	Feb 2, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.

First claim

The invention claimed is:

1. A method for patterning a substrate, the method comprising:
receiving a substrate having first metal lines that alternate with first dielectric lines on a working surface of the substrate, the first metal lines and the first dielectric lines being uncovered and defining a planar surface together;
forming second dielectric lines on the first dielectric lines by selectively depositing a dielectric material on the first dielectric lines without depositing the dielectric material on the first metal lines, the second dielectric lines defining trenches leaving the first metal lines uncovered;
depositing a conformal film on the working surface of the substrate, the conformal film covering sidewalls and top surfaces of the second dielectric lines and covering top surfaces of the first metal lines, the conformal film providing a predetermined etch resistivity;
depositing a dielectric layer that fills the defined trenches, covers the second dielectric lines, and provides a planar surface to the working surface of the substrate;
forming a first relief pattern above the dielectric layer, the first relief pattern defining locations of second metal lines to be transferred into the dielectric layer;
forming a second relief pattern above the dielectric layer, the second relief pattern defining locations of vias to be transferred into the dielectric layer;
transferring the second relief pattern into the dielectric layer by using the second relief pattern as a first etch mask and etching through the dielectric layer stopping on the conformal film above the first metal lines, the conformal film preventing etching of the second dielectric lines and the first metal lines uncovered by the second relief pattern; and
transferring the first relief pattern into the dielectric layer by using the first relief pattern as a second etch mask and etching into the dielectric layer stopping on top surfaces of the second dielectric lines using the conformal film as an etch stop layer.

2. The method of claim 1 , further comprising:
removing the second relief pattern and the first relief pattern; and
metallizing the dielectric layer by filling trenches and vias, defined by the dielectric layer, with a predetermined metal.

3. The method of claim 1 , further comprising, subsequent to removing the second relief pattern and the first relief pattern, removing uncovered portions of the conformal film such that top surfaces of the first metal lines are uncovered.

4. The method of claim 1 , wherein the first dielectric lines, the second dielectric lines, and the dielectric layer is comprised of a same material.

5. The method of claim 1 , wherein forming the first relief pattern includes forming the first relief pattern in a hardmask layer deposited above the dielectric layer.

6. The method of claim 1 , wherein forming the second relief pattern above the dielectric layer includes forming the second relief pattern above the first relief pattern.

7. The method of claim 1 , wherein forming the second relief pattern above the dielectric layer includes forming the second relief pattern in plane with the first relief pattern.

8. The method of claim 7 , wherein forming the second relief pattern in plane with the first relief pattern includes executing a freeze operation that prevents subsequent solubility changes of the first relief pattern.

9. The method of claim 2 , wherein the predetermined metal is copper.

10. The method of claim 2 , wherein metallizing the dielectric layer includes removing an overburden of the predetermined metal above a top surface of the dielectric layer.

Assignees

• Tokyo Electron Ltd

Inventors

• Smith Jeffrey
• Devilliers Anton J

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title