Deferred fractional memory row activation

Patent metadata

Field	Value
Publication number	US-11270741-B2
Application number	US-202017065278-A
Country	US
Kind code	B2
Filing date	Oct 7, 2020
Priority date	Jul 27, 2011
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

First claim

What is claimed is:

1. A method of operation within a memory controller component, the method comprising:
transmitting a first address to a memory component; and
transmitting one or more commands instructing the memory component to:
decode the first address to select a row of storage cells within a storage array of the memory component;
decode a subrow address to select a first subrow of data within the row of storage cells;
transfer the first subrow of data to a sense amplifier bank of the memory component;
decode a column address to select, within the sense amplifier bank, a first column of data within the first subrow of data; and
transfer the first column of data from the sense amplifier bank to output driver circuitry of the memory component to effect transmission of the first column of data to the memory controller component.

2. The method of claim 1 further comprising transmitting a second address to the memory component, the second address containing, within respective fields thereof, the subrow address and the column address.

3. The method of claim 2 further comprising generating a clock signal, and wherein transmitting the one or more commands and the first and second addresses to the memory component comprises:
transmitting a row command and the first address to the memory component during a first interval substantially equal to a period of the clock signal; and
transmitting a first column command and the second address to the memory component during a second interval also having a duration substantially equal to a period of the clock signal and that commences after the first interval has transpired.

4. The method of claim 3 wherein the first and second intervals are consecutive such that the second interval commences at the conclusion of the first interval.

5. The method of claim 3 wherein transmitting the first column command and the second address to the memory component comprises transmitting the first column command and the second address to the memory component a predetermined time after transmitting the row command to the memory component to effect receipt of the first column command and the second address within the memory component after decoding of the first address has commenced within the memory component.

6. The method of claim 3 further comprising transmitting a second column command and a third address to the memory component after transmitting the first column command and the second address, the second column command instructing the memory component to:
decode a subrow address included within the third address to select a second subrow of data within the row of storage cells; and
transfer the second subrow of data to the sense amplifier bank.

7. The method of claim 6 wherein transmitting the first and second column commands respectively instructing the memory component to transfer the first and second subrows of data to the sense amplifier bank comprises instructing the memory component to transfer the first and second subrows of data to respective first and second sets of sense amplifiers within the sense amplifier bank.

8. The method of claim 6 wherein transmitting the first column command, second address, second column command and third address to the memory component comprises:
transmitting the first column command and the first column address to the memory component a first predetermined time after transmitting the row command such that the memory component receives the first column command and the second address after decoding of the row address has commenced within the memory component; and
transmitting the second column command and the third address to the memory component a second predetermined time after transmitting the first column command and second address, the second predetermined time nominally matching the first predetermined time.

9. The method of claim 3 wherein transmitting the row command to the memory component comprises transmitting, as part of the row command, an operation code that specifies a precharge operation.

10. The method of claim 9 wherein transmitting the operation code that specifies the precharge operation comprises instructing the memory component to decouple bitlines of the storage array from individual storage cells within a row of storage cells identified in connection with a memory access operation commanded prior to transmitting the row command and row address.

11. The method of claim 3 further comprising transmitting to the memory component a bank address associated with the row command, and wherein transmitting the row command that instructs the memory component to decode the first to identify the row of storage cells within the storage array comprises:
instructing the memory component to identify, by decoding the bank address, one of a plurality of memory banks within the memory component; and
instructing the memory component to identify the row of storage cells within the identified one of the plurality of memory banks.

12. A memory controller component comprising:
a transaction queue;
command/address circuitry to transmit, in response to information within the transaction queue, a first address and one or more commands to a memory component, the one or more commands instructing the memory component to:
decode the first address to select a row of storage cells within a storage array of the memory component;
decode a subrow address to select a first subrow of data within the row of storage cells;
transfer the first subrow of data to a sense amplifier bank of the memory component;
decode a column address to select, within the sense amplifier bank, a first column of data within the first subrow of data; and
transfer the first column of data from the sense amplifier bank to output driver circuitry of the memory component to effect transmission of the first column of data to the memory controller component.

13. The memory controller component of claim 12 wherein the command/address circuitry to transmit the one or more commands and the first address to the memory component comprises circuitry to transmit a second address to the memory component, the second address containing, within respective fields thereof, the subrow address and the column address.

14. The memory controller component of claim 13 further comprising clock generation circuitry to generate a clock signal, and wherein the command/address circuitry to transmit the one or more commands and the first and second addresses to the memory component comprises circuitry to:
transmit a row command and the first address to the memory component during a first interval substantially equal to a period of the clock signal; and
transmit a first column command and the second address to the memory component during a second interval also having a duration substantially equal to a period of the clock signal and that commences after the first interval has transpired.

15. The memory controller component of claim 14 wherein the first and second intervals are consecutive such that the second interval commences at the conclusion of the first interval.

16. The memory controller component of claim 14 wherein the circuitry to transmit the first column command and the second address to the memory component comprises circuitry to transmit the first column command and the second address to the memory component a predetermined time after transmitting the row command to the memory component to effect receipt of the first column command and the second address within the memory component after decoding of the first address has commenced within the memory compo

Assignees

• Rambus Inc

Inventors

• Harris James E
• Vogelsang Thomas
• Ware Frederick A
• Shaeffer Ian P

Classifications

• G11C7/08

  Control thereof · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title