Memory with deferred fractional row activation

Patent metadata

Field	Value
Publication number	US-9330735-B2
Application number	US-201213640084-A
Country	US
Kind code	B2
Filing date	Jun 8, 2012
Priority date	Jul 27, 2011
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the sub-row to be activated.

First claim

What is claimed is:

1. A method of operation within a memory component, the method comprising:
receiving, during a first command reception interval, a row command and a row address, the row address indicating a row of storage cells within the memory component;
decoding the row address upon receiving the row command to select a row of storage cells within the memory component;
receiving, during a second command reception interval and after decoding the row address has commenced, a first column command and a first column address, the first column address indicating a first column of data within a first subrow of storage cells included within the row of storage cells, and the first column command indicating a memory access operation to be carried out with respect to the first column of data; and
transferring a first subrow of data, including the first column of data, from the first subrow of storage cells to a first set of sense amplifiers in response to the first column command.

2. The method of claim 1 further comprising executing the memory access operation indicated by the first column command with respect to the first column of data after transferring the first subrow of data from the first subrow of storage cells to the first set of sense amplifiers.

3. The method of claim 2 wherein executing the memory access operation comprises transferring the first column of data from the first set of sense amplifiers to an output driver of the memory component in a memory read operation, the output driver to output the first column of data from the memory component, wherein an elapsed time between receipt of the first column command and outputting the first column of data from the memory component comprises an activation interval during which the first subrow of data is transferred from the first subrow of storage cells to the first set of sense amplifiers and a column access interval during which the first column of data is transferred from the first set of sense amplifiers to the output driver.

4. The method of claim 2 wherein executing the memory access operation comprises transferring write data received via a data receiver of the memory component to the first set of sense amplifiers to overwrite the first column of data in a memory write operation.

5. The method of claim 1 wherein the row of storage cells comprises a plurality of subrows of storage cells coupled to respective sub-word lines, the plurality of subrows of storage cells including the first subrow of storage cells, and wherein transferring the first subrow of data from the first subrow of storage cells to the first set of sense amplifiers comprises asserting one of sub-word lines coupled to the first subrow of storage cells.

6. The method of claim 5 wherein asserting one of the sub-word lines comprises decoding at least a portion of the column address received during the second command reception interval to assert a first enable signal that corresponds to the one of the sub-word lines, wherein asserting one of the sub-word lines comprises decoding the row address to assert a second enable signal that, in combination with the first enable signal, enables assertion of the one of the sub-word lines.

7. The method of claim 1 further comprising receiving, during a third command reception interval that occurs later than the second command reception interval, a second column command and a second column address, the second column address indicating a second column of data within the first subrow of storage cells, wherein transferring the first subrow of data to the first set of sense amplifiers in response to the first column command comprises transferring the second column of data to the first set of sense amplifiers.

8. The method of claim 1 further comprising:
receiving, during a third command reception interval that occurs later than the second command reception interval, a second column command and a second column address, the second column address indicating a second column of data within a second subrow of storage cells included within the number of the storage cells coupled to the one of the sub-word lines; and
transferring the second subrow of data, including the second column of data, from the second subrow of storage cells to a second set of sense amplifiers in response to the second column command.

9. The method of claim 8 further comprising transferring the first column of data from the first set of sense amplifiers to an output driver of the memory component in response to the first column command and transferring the second column of data from the second set of sense amplifiers to the output driver of the memory component in response to the second column command, the output driver outputting the first column of data during a first output interval and outputting the second column of data during a second output interval that follows the first output interval.

10. A memory component comprising:
a plurality of storage cells;
command/address logic to receive a row command and a row address during a first command reception interval, and to receive a first column command and first column address during a second command reception interval that occurs later than the first command reception interval, the row address indicating a first row of the storage cells and the first column address indicating a first subrow of the storage cells included within the row, and the first column command indicating a memory access operation to be carried out with respect to a first column of data within the first subrow of the storage cells;
sense amplifiers coupled to respective storage cells within the row of the storage cells; and
row logic that decodes the row address starting at a time prior to receipt of the column command to assert a control signal corresponding to the row of storage cells; and
access logic to apply at least a portion of the first column address in combination with the control signal to enable data within the first subrow of the storage cells, including the first column of data, to be transferred to a first subset of the sense amplifiers.

11. The memory component of claim 10 further comprising output driver circuitry coupled to the access logic, and wherein the access logic further comprises a column decoder to select, according to the first column address, the first column of data within the first subset of the sense amplifiers to be output from the memory component via the output driver circuitry if the first column command indicates a column read operation, wherein an elapsed time between receipt of the first column command and output of the first column of data from the memory component comprises an activation interval during which the first column of data is transferred from the first subrow of the storage cells to the first subset of the sense amplifiers and a column access interval during which the first column of data is transferred from the first subset of the sense amplifiers to the output driver circuitry.

12. The memory component of claim 10 further comprising receiver circuitry coupled to the access logic, and wherein the access logic comprises a column decoder to select, according to the first column address, the first column of data within the first subset of the sense amplifiers to be overwritten by write data received within the memory component via the receiver circuitry if the first column command indicates a column write operation.

13. The memory component of claim 10 wherein the row logic that decodes the row address to assert a control signal corresponding to the row of storage cells comprises a plurality of global word lines and circuitry to assert the control signal on

Assignees

• Harris James Edward
• Vogelsang Thomas
• Ware Frederick A
• Shaeffer Ian P
• Rambus Inc

Inventors

• Harris James Edward
• Vogelsang Thomas
• Ware Frederick A
• Shaeffer Ian P

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/06 Primary

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title