Memory with deferred fractional row activation

Patent metadata

Field	Value
Publication number	US-10388337-B2
Application number	US-201815889191-A
Country	US
Kind code	B2
Filing date	Feb 5, 2018
Priority date	Jul 27, 2011
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

First claim

What is claimed is:

1. A method of operation within a memory component having a storage array and sense amplifier bank, the method comprising:
receiving a row command, row address, first column command and first column address;
precharging the storage array in response to the row command;
a predetermined time after receiving the row command, decoding the row address in response to the row command to identify a row of storage cells within the storage array;
decoding the first column address in response to the first column command to select a first subrow of data within the identified row of storage cells and to enable the first subrow of data to be transferred to the sense amplifier bank; and
further decoding the first column address to select, from within the sense amplifier bank, a first column of data within the first subrow and to enable the first column of data to be output from the memory component.

2. The method of claim 1 further comprising receiving a clock signal, and wherein receiving the row command, row address, first column command and first column address comprises:
receiving the row command and row address during a first command-address interval having a duration substantially equal to a period of the clock signal; and
receiving the first column command and first column address during a second command-address interval also having a duration substantially equal to a period of the clock signal and that commences after the first command-address interval has transpired.

3. The method of claim 2 wherein the first and second command-address intervals are consecutive such that the second command-address interval commences at the conclusion of the first command-address interval.

4. The method of claim 1 wherein precharging the storage array in response to the row command comprises precharging the storage array over a precharge interval, and wherein receiving the first column command and first column address comprises receiving the first column command and first column address prior to conclusion of the precharge interval.

5. The method of claim 1 further comprising:
receiving a second column command and a second column address after receiving the first column command and the first column address; and
decoding the second column address in response to the second column command to select a second subrow of data within the identified row of storage cells and to enable the second subrow of data to be transferred to the sense amplifier bank.

6. The method of claim 5 wherein decoding the first column address in response to the first column command to enable the first subrow of data to be transferred to the sense amplifier bank comprises transferring the first subrow of data to a first set of sense amplifiers within the sense amplifier bank, and wherein decoding the second column address in response to the second column command to enable the second subrow of data to be transferred to the sense amplifier bank comprises transferring the second subrow of data to a second set of sense amplifiers within the sense amplifier bank such that the first and second subrows of data are resident concurrently within the sense amplifier bank.

7. The method of claim 5 wherein precharging the storage array in response to the row command comprises precharging the storage array over a precharge interval, and wherein (i) receiving the first column command and first column address comprises receiving the first column command and first column address prior to conclusion of the precharge interval, and (ii) receiving the second column command and second column address comprises receiving the second column command and second column address prior to conclusion of the precharge interval.

8. The method of claim 1 wherein precharging the storage array in response to the row command comprises precharging the storage array in response to an operation code within the row command that specifies a precharge operation.

9. The method of claim 1 wherein precharging the storage array in response to the row command comprises decoupling bitlines of the storage array from individual storage cells within a row of storage cells identified in connection with a memory access operation commanded prior to receiving the row command and row address.

10. The method of claim 1 further comprising receiving a bank address associated with the row command, and wherein precharging the storage array comprises:
decoding the bank address in response to the row command to identify one of a plurality of memory banks within the memory component; and
precharging the one of the plurality of memory banks in response to the row command.

11. A memory component comprising:
a storage array;
a sense amplifier bank; and
access circuitry to:
receive a row command, row address, first column command and first column address;
precharge the storage array in response to the row command;
a predetermined time after receiving the row command, decode the row address in response to the row command to identify a row of storage cells within the storage array;
decode the first column address in response to the first column command to select a first subrow of data within the identified row of storage cells and to enable the first subrow of data to be transferred to the sense amplifier bank; and
further decode the first column address to select, from within the sense amplifier bank, a first column of data within the first subrow and to enable the first column of data to be output from the memory component.

12. The memory component of claim 11 further comprising circuitry to receive a clock signal, and wherein the access circuitry to receive the row command, row address, first column command and first column address comprises circuitry to:
receive the row command and row address during a first command-address interval having a duration substantially equal to a period of the clock signal; and
receive the first column command and first column address during a second command-address interval also having a duration substantially equal to a period of the clock signal and that commences after the first command-address interval has transpired.

13. The memory component of claim 12 wherein the first and second command-address intervals are consecutive such that the second command-address interval commences at the conclusion of the first command-address interval.

14. The memory component of claim 11 wherein the access circuitry to precharge the storage array in response to the row command and to receive the first column command and first column address comprises circuitry to (i) precharge the storage array over a precharge interval, and (ii) receive the first column command and first column address prior to conclusion of the precharge interval.

15. The memory component of claim 11 wherein the access circuitry additionally receives a second column command and a second column address after receiving the first column command and the first column address, and decodes the second column address in response to the second column command to select a second subrow of data within the identified row of storage cells and to enable the second subrow of data to be transferred to the sense amplifier bank.

16. The memory component of claim 15 the access circuitry to enable the first and second subrows of data to be transferred to the sense amplifier bank comprises circuitry to transfer the first subrow of data to a first set of sense amplifiers within the sense amplifier bank and to transfer the second subrow of data to a second set of sense amplifiers within the sense amplifier

Assignees

• Rambus Inc

Inventors

• Harris James E
• Vogelsang Thomas
• Ware Frederick A
• Shaeffer Ian P

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1039 Primary

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title