Memory with deferred fractional row activation

Patent metadata

Field	Value
Publication number	US-9570126-B2
Application number	US-201615138424-A
Country	US
Kind code	B2
Filing date	Apr 26, 2016
Priority date	Jul 27, 2011
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

First claim

What is claimed is:

1. A method of operation within a memory component, the method comprising:
receiving:
a row command and a row address, the row address indicating a row of storage cells within the memory component, and
a first column command and a first column address, the first column address indicating a first column of data within a first subrow of storage cells included within the row of storage cells, and the first column command indicating a memory access operation to be carried out with respect to the first column of data;

transferring a first subrow of data, including the first column of data, from the first subrow of storage cells to a first set of sense amplifiers in response to the first column command; and
precharging bit lines coupled to the first subrow of storage cells a predetermined time after receiving the first column command if the first column command specifies an auto-precharge.

2. The method of claim 1 wherein precharging bit lines coupled to the first subrow of storage cells comprises clearing the first subrow of data from the first set of sense amplifiers.

3. The method of claim 1 further comprising executing the memory access operation indicated by the first column command with respect to the first column of data after transferring the first subrow of data from the first subrow of storage cells to the first set of sense amplifiers.

4. The method of claim 3 wherein executing the memory access operation comprises transferring the first column of data from the first set of sense amplifiers to an output driver of the memory component in a memory read operation, the output driver to output the first column of data from the memory component, wherein an elapsed time between receipt of the first column command and outputting the first column of data from the memory component comprises an activation interval during which the first subrow of data is transferred from the first subrow of storage cells to the first set of sense amplifiers and a column access interval during which the first column of data is transferred from the first set of sense amplifiers to the output driver.

5. The method of claim 3 wherein executing the memory access operation comprises transferring write data received via a data receiver of the memory component to the first set of sense amplifiers to overwrite the first column of data in a memory write operation.

6. The method of claim 1 wherein the row of storage cells comprises a plurality of subrows of storage cells coupled to respective sub-word lines, the plurality of subrows of storage cells including the first subrow of storage cells, and wherein transferring the first subrow of data from the first subrow of storage cells to the first set of sense amplifiers comprises asserting one of sub-word lines coupled to the first subrow of storage cells.

7. The method of claim 6 wherein asserting one of the sub-word lines comprises decoding at least a portion of the first column address to assert a first enable signal that corresponds to the one of the sub-word lines, wherein asserting one of the sub-word lines comprises decoding the row address to assert a second enable signal that, in combination with the first enable signal, enables assertion of the one of the sub-word lines.

8. The method of claim 1 further comprising receiving a second column command and a second column address after receiving the first column command and first column address, the second column address indicating a second column of data within the first subrow of storage cells, wherein transferring the first subrow of data to the first set of sense amplifiers in response to the first column command comprises transferring the second column of data to the first set of sense amplifiers.

9. The method of claim 1 further comprising:
receiving a second column command and a second column address after receiving the first column command and first column address, the second column address indicating a second column of data within a second subrow of storage cells included within the number of the storage cells coupled to the one of the sub-word lines; and
transferring the second subrow of data, including the second column of data, from the second subrow of storage cells to a second set of sense amplifiers in response to the second column command.

10. The method of claim 9 further comprising transferring the first column of data from the first set of sense amplifiers to an output driver of the memory component in response to the first column command and transferring the second column of data from the second set of sense amplifiers to the output driver of the memory component in response to the second column command, the output driver outputting the first column of data during a first output interval and outputting the second column of data during a second output interval that follows the first output interval.

11. The method of claim 1 wherein receiving the row command and the row address comprises receiving the row command and the row address via a first transmission, and wherein receiving the column command and the column address comprises receiving the column command and the column address via a second transmission that succeeds the first transmission.

12. An integrated-circuit memory component comprising:
a plurality of storage cells;
command/address logic circuitry to receive:
a row command and a row address, the row address indicating a row of storage cells within the memory component, and
a first column command and a first column address, the first column address indicating a first column of data within a first subrow of storage cells included within the row of storage cells, and the first column command indicating a memory access operation to be carried out with respect to the first column of data; and

subrow activation circuitry to:
transfer a first subrow of data, including the first column of data, from the first subrow of storage cells to a first set of sense amplifiers in response to the first column command; and
precharge bit lines coupled to the first subrow of storage cells a predetermined time after receiving the first column command if the first column command specifies an auto-precharge.

13. The integrated-circuit memory component of claim 12 wherein the subrow activation circuitry to precharge bit lines coupled to the first subrow of storage cells comprises circuitry to clear the first subrow of data from the first set of sense amplifiers.

14. The integrated-circuit memory component of claim 12 further comprising column access circuitry to execute the memory access operation indicated by the first column command with respect to the first column of data the first subrow of data is transferred from the first subrow of storage cells to the first set of sense amplifiers.

15. The integrated-circuit memory component of claim 14 wherein the column access circuitry to execute the memory access operation comprises an output driver and circuitry to transfer the first column of data from the first set of sense amplifiers to the output driver in a memory read operation, the output driver to output the first column of data from the memory component, wherein an elapsed time between receipt of the first column command and outputting the first column of data from the memory component comprises an activation interval during which the first subrow of data is transferred from the first subrow of storage cells to the first set of sense amplifiers by the subrow activation circuitry and a column access interval during which the first column of data is transferred from the first set of sense amplifiers to th

Assignees

• Rambus Inc

Inventors

• Harris James E
• Vogelsang Thomas
• Ware Frederick A
• Shaeffer Ian P

Classifications

• G11C7/1039 Primary

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title