Memory with deferred fractional row activation

Patent metadata

Field	Value
Publication number	US-9911468-B2
Application number	US-201615390674-A
Country	US
Kind code	B2
Filing date	Dec 26, 2016
Priority date	Jul 27, 2011
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

First claim

What is claimed is:

1. A method of operation within a memory component having a storage array and sense amplifier bank, the method comprising:
sequentially receiving a row address, a first column address and a second column address;
decoding the row address to identify a row of storage cells within the storage array;
decoding the first column address to select a subrow of data within the identified row of storage cells and to enable the subrow of data to be transferred to the sense amplifier bank;
further decoding the first column address to select, from within the sense amplifier bank, a first column of data within the transferred subrow of data and to enable the first column of data to be output from the memory component; and
decoding the second column address to select, from within the sense amplifier bank, a second column of data within the transferred subrow of data and to enable the second column of data to be output from the memory component.

2. The method of claim 1 wherein decoding the first column address to enable the first column of data to be output from the memory component comprises enabling the first column of data to be output from the memory component with a first latency relative to receipt of the first column address, and wherein decoding the second column address to enable the second column of data to be output from the memory component comprises enabling the second column of data to be output from the memory component with a second latency relative to receipt of the second column address, the second latency being briefer than the first latency.

3. The method of claim 2 further comprising receiving a clock signal and wherein the second latency is briefer than the first latency by multiple cycles of the clock signal.

4. The method of claim 2 wherein the first latency is at least twice as long as second latency.

5. The method of claim 2 wherein the subrow of data from the identified row of storage cells is transferred to the sense amplifier bank over a time interval spanned by the first latency.

6. The method of claim 1 further comprising receiving first and second column read commands in association with first and second column addresses, respectively, and wherein decoding the first column address and the second column address comprises decoding the first and second column addresses in response to receipt of the first and second column read commands, respectively.

7. The method of claim 6 wherein the first column command and the second column command are distinguished by different operation codes that indicate respective first and second data output latencies for the first and second columns of data, the first data output latency corresponding to a time interval between receipt of the first column address and output of the first column of data and the second data output latency corresponding to a time interval between receipt of the second column address and output of the second column of data, the second data output latency being briefer than the first data output latency.

8. The method of claim 1 wherein sequentially receiving the row address, the first column address and the second column address comprises receiving the row address prior to receiving the first column address, and wherein decoding the row address comprises commencing decoding the row address prior to receiving the first column address.

9. The method of claim 1 wherein the sense amplifier bank comprises a smaller storage capacity than the identified row of storage cells.

10. The method of claim 1 wherein decoding the first column address to select the subrow of data comprises decoding most significant bits of the first column address, and wherein further decoding the first column address comprises decoding least significant bits of the first column address.

11. A memory component comprising:
a storage array;
a sense amplifier bank; and
access circuitry to:
sequentially receive a row address, a first column address and a second column address;
decode the row address to identify a row of storage cells within the storage array;
decode the first column address to select a subrow of data within the identified row of storage cells and to enable the subrow of data to be transferred to the sense amplifier bank;
further decode the first column address to select, from within the sense amplifier bank, a first column of data within the transferred subrow of data and to enable the first column of data to be output from the memory component; and
decode the second column address to select, from within the sense amplifier bank, a second column of data within the transferred subrow of data and to enable the second column of data to be output from the memory component.

12. The memory component of claim 11 wherein the access circuitry to decode the first and second column addresses to enable the first and second columns of data to be output from the memory component comprises circuitry to enable the first column of data to be output from the memory component with a first latency relative to receipt of the first column address and to enable the second column of data to be output from the memory component with a second latency relative to receipt of the second column address, the second latency being briefer than the first latency.

13. The memory component of claim 12 wherein the first latency is at least twice as long as second latency.

14. The memory component of claim 12 wherein the access circuitry to decode the first column address to enable the subrow of data from the identified row of storage cells to be transferred to the sense amplifier bank comprises circuitry to transfer the subrow of data from the identified row of storage cells to the sense amplifier bank over a time interval spanned by the first latency.

15. The memory component of claim 11 access circuitry to sequentially receive the row address, the first column address and the second column address comprises circuitry to receive first and second column read commands in association with first and second column addresses, respectively, and the access circuitry to decode the first column address and the second column address comprises circuitry to decode the first and second column address in response to receipt of the first and second column read commands, respectively.

16. The memory component of claim 15 wherein the first column command and the second column command are distinguished by different operation codes that indicate respective first and second data output latencies for the first and second columns of data, the first data output latency corresponding to a time interval between receipt of the first column address and output of the first column of data and the second data output latency corresponding to a time interval between receipt of the second column address and output of the second column of data, the second data output latency being briefer than the first data output latency.

17. The memory component of claim 11 wherein the access circuitry to decode the row address comprises circuitry to commence decoding the row address prior to receipt of the first column address.

18. The memory component of claim 11 wherein the sense amplifier bank comprises a smaller storage capacity than the identified row of storage cells.

19. The memory component of claim 11 wherein the access circuitry to decode the first column address to select the subrow of data comprises circuitry to decode most significant bits of the first column address, and wherein the access circuity to further decode the

Assignees

• Rambus Inc

Inventors

• Harris James E
• Vogelsang Thomas
• Ware Frederick A
• Shaeffer Ian P

Classifications

• G11C7/08

  Control thereof · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C8/10

  Decoders · CPC title

• G11C7/1039 Primary

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title