Defect classification and source analysis for semiconductor equipment

Patent metadata

Field	Value
Publication number	US-11263737-B2
Application number	US-201916245040-A
Country	US
Kind code	B2
Filing date	Jan 10, 2019
Priority date	Jan 10, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Defects on a substrate comprising electronic components can be classified with a computational defect analysis system that may be implemented in multiple stages. For example, a first stage classification engine may process metrology data to produce an initial classification of defects. A second stage classification engine may use the initial classification, along with manufacturing information and/or prior defect knowledge to output probabilities that the defects are caused by one or more potential sources.

First claim

What is claimed is:

1. A defect analysis computational system comprising:
(a) one or more processors;
(b) program instructions for executing on the one or more processors, the program instructions defining:
one or more first stage defect classification engines configured to:
receive metrology data acquired for defects on a substrate comprising electronic devices or partially fabricated electronic devices, wherein the metrology data includes an image, composition data, and/or a wafer map, and
produce a first stage defect classification from the metrology data; and

a second stage defect classification engine configured to:
receive the first stage defect classification produced by the one or more first stage defect classification engines,
receive manufacturing information comprising data about (i) a plurality of materials on the substrate, and (ii) prior defect classification for a manufacturing equipment and/or fabrication process,
determine, using the first stage defect classification and the manufacturing information, one or more sources of the defects on the substrate, and
output a likelihood of the defects being caused by a first source associated with the manufacturing equipment, one or more materials on the substrate, and/or fabrication process.

2. The defect analysis computational system of claim 1 , wherein the metrology data comprises the image, the composition data, and the wafer map.

3. The defect analysis computational system of claim 1 , wherein the metrology data comprises metadata pertaining to an inspection tool used in obtaining the metrology data.

4. The defect analysis computational system of claim 1 , wherein the first stage defect classification comprises a morphology classification for the defects on the substrate.

5. The defect analysis computational system of claim 1 , wherein the first stage defect classification comprises a composition classification for the defects on the substrate.

6. The defect analysis computational system of claim 1 , wherein the first stage defect classification comprises a wafer map classification for the defects on the substrate.

7. The defect analysis computational system of claim 1 , wherein the first stage defect classification engine comprises one or more neural networks.

8. The defect analysis computational system of claim 1 , wherein the manufacturing equipment is a dry etch reactor, a chemical vapor deposition reactor, an atomic layer deposition reactor, a physical vapor deposition reactor, or an electroplating reactor.

9. The defect analysis computational system of claim 1 , wherein the second stage defect classification engine is additionally configured to further classify the defects on the substrate.

10. The defect analysis computational system of claim 1 , wherein the second stage defect classification engine is additionally configured to provide suggested corrective actions to reduce generation of defects on the substrate and/or reduce occurrences of defects on substrates processed in the future.

11. The defect analysis computational system of claim 1 , wherein the second stage defect classification engine is configured to determine the one or more sources of defects on the substrate by using a Bayesian analysis.

12. The defect analysis computational system of claim 1 , wherein the metrology data was obtained in situ during the fabrication process.

13. The defect analysis computational system of claim 1 , wherein the one or more first stage defect classification engines are further configured to receive sensor data selected from the group consisting of environmental conditions of the fabrication process, change in the mass of the substrate during the fabrication process, mechanical forces experienced during the fabrication process, and combinations thereof, and wherein the second stage defect classification engine is further configured to determine the one or more sources of defects on the substrate using the sensor data.

14. A computational method of analyzing defects, the method comprising:
receiving metrology data acquired for defects on a substrate comprising electronic devices or partially fabricated electronic devices, wherein the metrology data includes an image, composition data, and/or a wafer map;
producing a first stage defect classification from the metrology data;
receiving manufacturing information comprising data (i) a plurality of materials on the substrate, and (ii) prior defect classification for a manufacturing equipment and/or fabrication process,
determining, using the first stage defect classification and the manufacturing information, one or more likely sources of the defects on the substrate, and
outputting a likelihood of the defects being caused by a first source associated with the manufacturing equipment, one or more materials on the substrate, and/or fabrication process.

15. The method of claim 14 wherein the metrology data comprises the image, the composition data, and the wafer map.

16. The method of claim 14 , wherein the metrology data comprises metadata pertaining to an inspection tool used in obtaining the metrology data.

17. The method of claim 14 , wherein the first stage defect classification comprises a morphology classification for the defects on the substrate.

18. The method of claim 14 , wherein the first stage defect classification comprises a composition classification for the defects on the substrate.

19. The method of claim 14 , wherein the first stage defect classification comprises a wafer map classification for the defects on the substrate.

20. The method of claim 14 , wherein one or more neural networks produce the first stage defect classification from the metrology data.

21. The method of claim 14 , wherein the manufacturing equipment is a dry etch reactor, a chemical vapor deposition reactor, an atomic layer deposition reactor, a physical vapor deposition reactor, or an electroplating reactor.

22. The method of claim 14 , further comprising using the first stage defect classification and the manufacturing information, further classifying the defect on the substrate.

23. The method of claim 14 , further comprising using the first stage defect classification and the manufacturing information, providing suggested corrective actions to reduce generation of defects on the substrate and/or reduce occurrences of defects on substrates processed in the future.

24. The method of claim 14 , wherein determining one or more likely sources of the defects on the substrate comprises performing a Bayesian analysis.

25. The method of claim 14 , wherein the metrology data was obtained in situ during the fabrication process.

26. The method of claim 14 , further comprising receiving sensor data selected from the group consisting of environmental conditions of the fabrication process, change in the mass of the substrate during the fabrication process, mechanical forces experienced during the fabrication process, and combinations thereof, and determining the one or more likely sources of the defects on the substrate using the sensor data.

27. A computer program product for analyzing defects, the computer program product comprising a non-transitory computer readable medium on which is provided computer executable instructions for:
receiving metrology data acquired for defects on a substrate comprising electronic devices or partially fabricated electronic devices, wherein the

Assignees

• Lam Res Corp

Inventors

• Sawlani Kapil
• Gottscho Richard A
• Danek Michal
• Wells Keith
• Hansen Keith

Classifications

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/0616

  Monitoring of warpages, curvatures, damages, defects or the like · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G01N21/8851

  Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges (G01N21/8806 and G01N21/93 - G01N21/95692 take precedence; optical measurement of dimensions G01B11/00; optical scanning G02B26/10; image transformation G06T3/00; computerised image enhancement G06T5/00; image processing per se for flaw detection G06T7/0002) · CPC title

• G01N2021/8887

  based on image processing techniques · CPC title