Compensating for scanning electron microscope beam distortion-induced metrology error using design

Patent metadata

Field	Value
Publication number	US-10529534-B2
Application number	US-201815965061-A
Country	US
Kind code	B2
Filing date	Apr 27, 2018
Priority date	Jan 5, 2018
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Methods and systems for quantifying and correcting for non-uniformities in images used for metrology operations are disclosed. A metrology area image of a wafer and a design clip may be used. The metrology area image may be a scanning electron microscope image. The design clip may be the design clip of the wafer or a synthesized design clip. Tool distortions, including electron beam distortions, can be quantified and corrected. The design clip can be applied to the metrology area image to obtain a synthesized image such that one or more process change variations are suppressed and one or more tool distortions are enhanced.

First claim

What is claimed is:

1. A method of compensating for scanning electron microscope beam distortion-induced metrology error comprising:
receiving, at a processor, a metrology area image of a wafer, wherein the metrology area image is a microscopy image of the wafer;
receiving, at the processor, a design clip from a storage medium, wherein the design clip includes one or more design polygons and corresponds to an area of the wafer in the metrology area image;
applying the design clip to the metrology area image using the processor with an image comparison and rendering process thereby obtaining a synthesized image, wherein one or more process change variations are suppressed and one or more tool distortions are enhanced; and
performing metrology operations on the synthesized image.

2. The method of claim 1 , wherein the design clip is a design for the wafer.

3. The method of claim 1 , wherein the design clip is a synthesized design clip, and wherein the synthesized design clip is generated by a method comprising:
generating the synthesized design clip using the process change variations with a machine algorithm; and
communicating the synthesized design clip to the storage medium.

4. The method of claim 3 , wherein the synthesized design clip is generated by a method further comprising:
receiving images and data from one or more process modulated wafers at a machine learning module; and
learning the process change variations at the machine learning module using the machine algorithm.

5. The method of claim 3 , wherein the machine algorithm is a deep learning algorithm.

6. The method of claim 1 , wherein the metrology area image is a scanning electron microscope image.

7. The method of claim 1 , wherein the metrology area image is an average of a plurality of scanning electron microscope images.

8. The method of claim 1 , wherein the storage medium is a persistent, non-transient storage medium.

9. The method of claim 1 , further comprising obtaining the metrology area image of the wafer using a scanning electron microscope.

10. The method of claim 1 , further comprising tuning system components of a wafer metrology tool to reduce distortion based on the metrology operations.

11. A system for compensating for distortion-induced metrology error comprising:
a wafer metrology tool configured to produce a metrology area image, wherein the metrology area image is a microscopy image of the wafer; and
a processor in electronic communication with the wafer metrology tool, wherein the processor is configured to receive and apply a design clip to the metrology area image using an image comparison and rendering process such that one or more process change variations are suppressed and one or more tool distortions are enhanced thereby obtaining a synthesized image, wherein the design clip includes one or more design polygons and corresponds to an area of the wafer in the metrology area image.

12. The system of claim 11 , wherein the wafer metrology tool is a scanning electron microscope.

13. The system of claim 11 , further comprising an electronic data storage medium containing the design clip, wherein the electronic data storage medium is in electronic communication with the processor.

14. The system of claim 11 , wherein the processor is further configured to perform metrology operations on the synthesized image.

15. The system of claim 11 , wherein the design clip is a synthesized design clip, and wherein the system includes a machine learning module that is configured to:
receive images and data from one or more process modulated wafers;
learn the process change variations using the images and data; and
generate the synthesized design clip using the process change variations.

16. A non-transitory computer-readable storage medium, comprising one or more programs for executing the following steps on one or more computing devices:
applying a design clip to a metrology area image using an image comparison and rendering process thereby obtaining a synthesized image, wherein one or more process change variations are suppressed and one or more tool distortions are enhanced, wherein the metrology area image is a microscopy image of the wafer, and wherein the design clip includes one or more design polygons and corresponds to an area of the wafer in the metrology area image; and
sending instructions to perform metrology operations on the synthesized image.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the design clip is a synthesized design clip, and wherein the steps include generating the synthesized design clip using the process change variations with a machine algorithm.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the machine algorithm is a deep learning algorithm.

19. The non-transitory computer-readable storage medium of claim 16 , wherein the metrology area image is a scanning electron microscope image.

20. The non-transitory computer-readable storage medium of claim 16 , wherein the metrology area image is an average of a plurality of scanning electron microscope images.

Assignees

• Kla Tencor Corp

Inventors

• Pathangi Sriraman Hari

Classifications

• H01J2237/2826

  Calibration · CPC title

• H01J2237/2817

  Pattern inspection · CPC title

• H01J2237/2814

  Measurement of surface topography · CPC title

• H01J37/222 Primary

  Image processing arrangements associated with the tube · CPC title

• G06T5/50 Primary

  using two or more images, e.g. averaging or subtraction · CPC title