Interconnect scaling

Patent metadata

Field	Value
Publication number	US-2017221815-A1
Application number	US-201715405344-A
Country	US
Kind code	A1
Filing date	Jan 13, 2017
Priority date	Jan 28, 2016
Publication date	Aug 3, 2017
Grant date	—

Abstract

Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.

First claim

What is claimed is:

1 . An interconnect structure comprising:
a first layer comprising:
a first insulator layer;
a first dielectric layer on the first insulator layer;
a subtractive etch feature comprising a first conductive material, the subtractive etch feature having a first subtractive etch vertical wall, a second subtractive etch vertical wall, and an angle between the first subtractive etch vertical wall and a horizontal plane that is less than 90 degrees; and
a damascene feature comprising a second conductive material, the damascene feature having a first damascene vertical wall, a second damascene vertical wall, and an angle between the first damascene vertical wall and the horizontal plane that is greater than 90 degrees;
wherein the first subtractive etch vertical wall is parallel to the second damascene vertical wall; and
a second layer comprising:
a second insulator layer; and
a metal feature; and
a conductive via that extends from the second layer to the first layer.

2 . The interconnect structure according to claim 1 , wherein the metal feature comprises a second subtractive etch feature, the second subtractive etch feature comprising a third conductive material, the subtractive etch feature having a third subtractive etch vertical wall, a fourth subtractive etch vertical wall, and an angle between the third subtractive etch vertical wall and the horizontal plane that is less than 90 degrees,

3 . The interconnect structure according to claim 2 , wherein the conductive via that extends from the second layer to the first layer underlies the second subtractive etch feature.

4 . The interconnect structure according to claim 1 , wherein the metal feature comprises a second damascene feature, the second damascene feature comprising a third damascene vertical wall, a fourth damascene vertical wall, and an angle between the third damascene vertical wall and the horizontal plane that is greater than 90 degrees.

5 . The interconnect structure according to claim 1 , further comprising a third dielectric layer on top of the second insulator layer.

6 . The interconnect structure according to claim 5 , further comprising a fourth dielectric layer.

7 . The interconnect structure according to claim 1 , further comprising a metal liner.

8 . The interconnect structure according to claim 7 , wherein the metal feature is lined with the metal liner.

9 . The interconnect structure according to claim 1 , wherein the subtractive etch feature is lined with the metal liner.

10 . The interconnect structure according to claim 1 , wherein the damascene structure is lined with the metal liner.

11 . The interconnect structure according to claim 1 , wherein the first dielectric layer has a dielectric constant less than or equal to 4.

12 . The interconnect structure according to claim 1 , wherein the first dielectric layer comprises silicon dioxide.

13 . The interconnect structure according to claim 1 , wherein the first dielectric layer comprises carbon doped oxide.

14 . The interconnect structure according to claim 1 , wherein the first dielectric layer is a composite layer.

15 . The interconnect structure according to claim 14 , wherein the first dielectric layer comprises an adhesion layer.

16 . The interconnect structure according to claim 14 , wherein the first dielectric layer comprises an etch stop layer.

17 . The interconnect structure according to claim 14 , wherein the first dielectric layer comprises nitrogen.

18 . The interconnect structure according to claim 14 , wherein the first dielectric layer comprises a porous layer.

19 . The interconnect structure of claim 1 , further comprising a second via.

20 . The interconnect structure of claim 19 , wherein the second via extends from the first dielectric layer through the first insulator layer to a third layer.

Assignees

• IBM

Inventors

• Bonilla Griselda
• Choi Samuel S
• Filippi Ronald G
• Huang Elbert E
• Lustig Naftali E
• Simon Andrew H

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/264

  by chemical means · CPC title