Trap layer substrate stacking technique to improve performance for RF devices

Patent metadata

Field	Value
Publication number	US-9761546-B2
Application number	US-201615051197-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	Oct 19, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

First claim

What is claimed is:

1. A method, comprising:
providing a first substrate that includes a first handle substrate, an insulating layer disposed over the first handle substrate, and a semiconductor layer disposed over the insulating layer;
forming an interconnect structure over the first substrate, wherein the interconnect structure includes a plurality of metal layers disposed within a dielectric structure;
bonding a second substrate, which includes a second handle substrate and a trapping layer, to an upper surface of the interconnect structure, wherein after bonding the trapping layer is disposed between the second handle substrate and the upper surface of the interconnect structure; and
after the bonding, removing the first handle substrate to expose a lower surface of the insulating layer.

2. The method of claim 1 , further comprising:
after removing the first handle substrate, forming a contact pad in direct physical contact with the lower surface of the insulating layer of the first substrate, wherein a through-substrate-via (TSV) extends vertically through the semiconductor layer and insulating layer and electrically couples the contact pad to a metal layer of the interconnect structure.

3. The method of claim 1 , wherein the first and second handle substrates have different ohmic resistances.

4. The method of claim 1 , wherein the first handle substrate has a resistance of between 8 ohm-cm and 12 ohm-cm.

5. The method of claim 1 , wherein the first handle substrate has a first ohmic resistance and the second handle substrate has a second ohmic resistance, the second ohmic resistance being greater than the first ohmic resistance by a factor of ten or more.

6. The method of claim 1 , wherein the second handle substrate comprises a silicon substrate and the trapping layer comprises an amorphous silicon layer.

7. The method of claim 1 , wherein the second handle substrate comprises a silicon substrate and the trapping layer comprises a polysilicon layer that meets the silicon substrate at a non-planar interface.

8. The method of claim 7 , wherein the non-planar interface comprises a series of peaks extending downwardly from the silicon substrate into the trapping layer.

9. The method of claim 7 , wherein the non-planar interface is formed by forming a photomask over a surface of the silicon substrate and etching the surface of the silicon substrate to form a series of peaks and valleys, and the trapping layer is formed directly over the series of peaks and valleys.

10. The method of claim 1 , wherein a radio-frequency (RF) device is arranged in the interconnect structure and is configured to transmit an RF signal, wherein the trapping layer is configured to trap carriers excited by the RF signal to limit Eddy currents in the second handle substrate.

11. A method, comprising:
providing a semiconductor-on-insulator (SOI) substrate that includes a first handle substrate of silicon, an insulating layer disposed over the first handle substrate, and a silicon layer disposed over the insulating layer, wherein the SOI substrate includes a transistor device region and a radio-frequency (RF) region which are spaced laterally apart from one another;
forming an interconnect structure over the SOI substrate, wherein the interconnect structure includes a plurality of metal layers disposed within a dielectric structure;
bonding a second substrate, which includes a trapping layer and a second handle substrate made of silicon, to an upper surface of the interconnect structure, wherein after bonding the trapping layer separates the second handle substrate from the upper surface of the interconnect structure;
after the bonding, removing the first handle substrate to expose a lower surface of the insulating layer; and
forming a contact pad in direct contact with the lower surface of the insulating layer, wherein a through-substrate-via (TSV) extends vertically through the silicon layer and through the insulating layer to contact the contact pad.

12. The method of claim 11 , wherein the first handle substrate has an ohmic resistance that is less than the second handle substrate.

13. The method of claim 11 , further comprising:
forming a gate dielectric on an upper surface of the transistor device region of the silicon layer; and
forming a gate electrode over the gate dielectric, wherein at least one of the metal layers is coupled to the gate electrode.

14. The method of claim 13 , wherein the TSV electrically couples the contact pad to the at least one of the metal layers.

15. A method, comprising:
providing a first substrate comprising a semiconductor layer disposed over an insulating layer, wherein the first substrate includes a transistor device region and a radio-frequency (RF) region;
forming an interconnect structure over the first substrate, the interconnect structure including a plurality of metal layers disposed within a dielectric structure; and
bonding a second substrate, which includes a handle substrate and a trapping layer, disposed over an upper surface of the interconnect structure;
wherein the trapping layer separates the second substrate from the interconnect structure, and wherein the trapping layer is made of polysilicon and directly contacts the handle substrate at an interface made up of a series of peaks.

16. The method of claim 15 , further comprising:
forming a through substrate via extending vertically through the semiconductor layer and the insulating layer; and
forming a contact pad on a lower surface of the insulating layer of the first substrate, the contact pad electrically coupled to a metal layer of the interconnect structure through the through substrate via.

17. The method of claim 16 , further comprising:
forming a packaging layer covering the lower surface of the insulating layer and extending along sidewalls of the interconnect structure to cover an upper surface of the handle substrate.

18. The method of claim 15 , wherein the RF region includes an RF device arranged in the interconnect structure and configured to transmit an RF signal, wherein the trapping layer is configured to trap carriers excited by the RF signal to limit Eddy currents in the handle substrate.

19. The method of claim 15 , wherein the series of peaks at the interface is formed by forming a photomask over a surface of the handle substrate and etching the surface of the handle substrate to form a series of peaks and valleys, and the trapping layer is formed directly over the series of peaks and valleys.

20. The method of claim 15 , wherein the first substrate comprises a first handle substrate, wherein the insulating layer is disposed over the first handle substrate, and the semiconductor layer is disposed over the insulating layer; and wherein the first handle substrate has a first ohmic resistance of between 8 ohm-cm and 12 ohm-cm and the handle substrate of the second substrate has a second ohmic resistance, the second ohmic resistance being greater than the first ohmic resistance by a factor of ten or more.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Kuo-Yu
• Chao Chih-Ping
• Tsai Kuan-Chi
• Chen Shih-Shiung
• Tsai Wei-Kung

Classifications

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title