Solder mask for thermal pad of a printed circuit board to provide reliable solder contact to an integrated circuit

US11244892B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11244892-B2
Application numberUS-201916550775-A
CountryUS
Kind codeB2
Filing dateAug 26, 2019
Priority dateAug 30, 2018
Publication dateFeb 8, 2022
Grant dateFeb 8, 2022

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming a solder connection includes forming a solder mask on a thermal pad of a printed circuit board. The solder mask leaves unmasked portions of the thermal pad and forming the solder mask includes forming a plurality of mask stripes extending from edges of each unmasked portion towards a center of the unmasked portion. The method includes depositing solder paste on the unmasked portions of the thermal pad and placing an exposed thermal pad of an integrated circuit package on the solder paste deposited on the thermal pad of the printed circuit board. The method includes forming a solder connection by heating the solder paste between the unmasked portions of the thermal pad on the printed circuit board and the exposed thermal pad of the integrated circuit package.

First claim

Opening claim text (preview).

The invention claimed is: 1. A printed circuit board, comprising: a thermal pad; and a solder mask that leaves portions of the thermal pad unmasked leaving exposed a plurality of unmasked portions of the thermal pad from the solder mask, each one of the plurality of unmasked portions of the thermal pad each including a plurality of edges, and the solder mask including a plurality of mask stripes extending from the plurality of edges of the plurality of unmasked portions, each one of the plurality of mask stripes extends towards a corresponding center of one of the unmasked portions. 2. The printed circuit board of claim 1 , wherein the plurality of mask stripes include orthogonal mask stripes extending from the edges of each unmasked portion towards the corresponding center of one of the unmasked portions. 3. The printed circuit board of claim 1 , wherein each unmasked portion includes a plurality of corners, and wherein the plurality of mask stripes include angled corner mask stripes extending from the corners towards the corresponding center of one of the unmasked portions. 4. The printed circuit board of claim 1 , wherein each of the unmasked portions includes a plurality of corners, and wherein the plurality of mask stripes include corner mask stripes in each corner of each one of the unmasked portions. 5. A device, comprising: a thermal pad includes a surface; a solder mask on the surface of the thermal pad, the solder mask including: a first portion extending in a first direction; a second portion extending in a second direction transverse to the first direction, the first portion and the second portion extend across each other; a third portion surrounding the first portion and the second portion; and a first extension portion extends from the third portion toward the second portion of the solder mask; an exposed portion of the thermal pad exposed from the solder mask, the exposed portion of the thermal pad surrounded by the first, second, and third portions of the solder mask, and wherein the first extension portion extends into the exposed portion of the thermal pad. 6. The device of claim 5 , wherein the exposed portion is a square region. 7. The device of claim 6 , wherein the solder mask further includes a second extension portion that extends from the third portion of the solder mask towards the first portion of the solder mask, the second extension portion extends into the square region. 8. The device of claim 7 , wherein the first extension portion has an end that terminates between the first, second, and third portions of the solder mask. 9. The device of claim 5 , wherein the first extension portion of the solder mask has an end that terminates before the first extension portion extends to the second portion of the solder mask. 10. The device of claim 9 , wherein the end of the first extension portion is between the first, second, and third portions of the solder mask. 11. The device of claim 5 , wherein the solder mask further includes a second extension portion that extends from the third portion, the extension portion being at a first angle to the first portion of the solder mask and at a second angle to the second portion of the solder mask. 12. The device of claim 11 , wherein the first angle is substantially equal to the second angle. 13. The device of claim 12 , wherein the exposed portion is a square region having a corner, and the second extension portion extends into the corner of the square region. 14. The device of claim 11 , wherein the first angle is greater than the second angle. 15. The device of claim 11 , wherein the first angle is less than the second angle. 16. The device of claim 5 , wherein the solder mask further includes a second extension portion that extends between respective adjacent portions of the third portion. 17. A device, comprising: a thermal pad having a surface; a solder mask on the surface of the thermal pad, the solder mask including: a first cross-over portion extending in a first direction; a second cross-over portion extending in a second direction, the second cross-over portion crossing over the first cross-over portion; and a boundary portion that surrounds the first cross-over portion and the second cross-over portion, the first cross-over portion having first ends that terminate at the boundary portion, the second cross-over portion having second ends that terminate at the boundary portion; an exposed portion of the thermal pad exposed from the solder mask, the exposed portion of the thermal pad surrounded by the solder mask; a first plurality of vias are aligned with the boundary portion; a second plurality of vias are aligned with the first cross-over portion; and a third plurality of vias are aligned with the second cross-over portion. 18. The device of claim 17 , wherein the solder mask further includes a plurality of mask strip portions that extend outward from the first cross-over portion, the second cross-over portion, and the boundary portion towards the exposed portion of the thermal pad. 19. The device of claim 18 , wherein the plurality of mask strip portions further includes: a first mask strip portion parallel with the first cross-over portion; a second mask strip portion parallel with the second cross-over portion; a third mask strip portion at a first angle to the first cross-over portion and a second angle to the second cross-over portion; a fourth mask strip portion that extends between respective adjacent portions of the boundary portion.

Assignees

Inventors

Classifications

  • forming a chip-scale package [CSP] · CPC title

  • Bumps or wires · CPC title

  • specially adapted for cooling · CPC title

  • Bonding materials between chips and die pads · CPC title

  • Applying pastes or inks, e.g. screen printing (H10W70/095 takes precedence) · CPC title

Patent family

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External sources

Frequently asked questions

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What does patent US11244892B2 cover?
A method of forming a solder connection includes forming a solder mask on a thermal pad of a printed circuit board. The solder mask leaves unmasked portions of the thermal pad and forming the solder mask includes forming a plurality of mask stripes extending from edges of each unmasked portion towards a center of the unmasked portion. The method includes depositing solder paste on the unmasked …
Who is the assignee on this patent?
St Microelectronics Pte Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/479. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 08 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).