Two-part programming methods

Patent metadata

Field	Value
Publication number	US-9858991-B2
Application number	US-201615287956-A
Country	US
Kind code	B2
Filing date	Oct 7, 2016
Priority date	Nov 20, 2008
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.

First claim

What is claimed is:

1. A memory device, comprising:
control circuitry;
wherein the control circuitry is configured to cause the memory device to program a first memory cell to a first level using a first set of program pulses within a first programming voltage range;
wherein the control circuitry is configured to cause the memory device to inhibit a second memory cell to be programmed to a second level less than the first level while the memory device is caused to program the first memory cell to the first level;
wherein after the memory device is caused to program the first memory cell to the first level, the control circuitry is configured to cause the second memory cell to be programmed to the second level using a second set of program pulses within a second programming voltage range;
wherein the control circuitry is configured to cause the memory device to inhibit the first memory cell, that was caused to be programmed to the first level, while the memory device is caused to program the second memory cell to the second level;
wherein the first programming voltage range is different than the second programming voltage range; and
wherein the first programming voltage range overlaps the second programming voltage range.

2. The memory device of claim 1 , wherein the control circuitry is configured to cause the memory device to apply the first set of program pulses within the first programming voltage range to the second memory cell while the memory device is caused to inhibit the second memory cell while the memory device is caused to program the first memory cell to the first level using the first set of program pulses within the first programming voltage range, and wherein the control circuitry is configured to cause the memory device to apply the second set of program pulses within the second programming voltage range to the first memory cell while the memory device is caused to inhibit the first memory cell while the memory device is caused to program the second memory cell to the second level using the second set of program pulses within the second programming voltage range.

3. The memory device of claim 1 , wherein while the memory device is caused to program the first memory cell to the first level using the first set of program pulses, the control circuitry is configured to cause the memory device to program a third memory cell to a third level greater than the first level using the first set of program pulses.

4. The memory device of claim 3 , wherein the first, second, and third memory cells are in a same page of memory cells.

5. The memory device of claim 1 , wherein the first programming voltage range comprises a start programming voltage that is greater than a start programming voltage of the second programming voltage range and that is less than a stop programming voltage of the second programming voltage range.

6. The memory device of claim 1 , wherein the first programming voltage range and the second programming voltage range overlap only at a program start voltage of the first programming voltage range and a program stop voltage of the second programming voltage range.

7. The memory device of claim 1 , wherein the first level is greater than or equal to a first particular level and the second level is less than or equal to a second particular level that is less than the first particular level.

8. A memory device, comprising:
control logic;
wherein the control logic is configured to cause the memory device to load data to be programmed to levels within a first plurality of levels that are greater than or equal to a particular level;
wherein the control logic is configured to cause the memory device to program first memory cells to the levels within the first plurality of levels using a first set of program pulses having programming voltages within a first programming voltage range;
wherein the control logic is configured to cause the memory device to inhibit programming of second memory cells to be programmed to levels within a second plurality of levels that are less than the particular level while the memory device is caused to program the first memory cells to the levels within the first plurality of levels;
after the memory device is caused to program the first memory cells to the levels within the first plurality of levels, the control logic is configured to cause the memory device to load data to be programmed to the levels within the second plurality of levels;
after the memory device is caused to program the first memory cells to the levels within the first plurality of levels, the control logic is configured to cause the memory device to program the second memory cells to the levels within the second plurality of levels using a second set of program pulses having programming voltages within a second programming voltage range;
wherein the control logic is configured to cause the memory device to inhibit programming of the first memory cells, that were caused to be programmed to the levels within the first plurality of levels, while the memory device is caused to program the second memory cells to the levels within the second plurality of levels;
wherein the first programming voltage range is different than the second programming voltage range; and
wherein the first programming voltage range overlaps the second programming voltage range.

9. The memory device of claim 8 , wherein the control logic being configured to cause the memory device to load the data to be programmed to the levels within the first plurality of levels comprises the control logic being configured to cause the memory device to load the data to be programmed to the levels within the first plurality of levels into latches that correspond to the first memory cells.

10. The memory device of claim 9 , wherein the control logic being configured to cause the memory device to inhibit programming of the first memory cells comprises the control logic being configured to cause the memory device to re-load the latches that correspond to the first memory cells with inhibit data.

11. The memory device of claim 8 , wherein the control logic being configured to cause the memory device to inhibit programming of the second memory cells comprises the control logic being configured to cause the memory device to load inhibit data into latches that correspond to the second memory cells.

12. The memory device of claim 11 , wherein the control logic being configured to cause the memory device to load data to be programmed to the levels within the second plurality of levels comprises the control logic being configured to cause the memory device to re-load the latches that correspond to the second memory cells with the data to be programmed to the levels within the second plurality of levels.

13. The memory device of claim 8 , wherein the first memory cells and the second memory cells are in a same page of memory cells.

14. The memory device of claim 8 , wherein the first programming voltage range comprises a start programming voltage that is within the second programming voltage range.

15. The memory device of claim 8 , wherein the particular level is a first particular level and wherein the second plurality of levels that are less than the first particular level comprises the second plurality of levels being less than or equal to a second particular level that is less than the first particular level.

16. The memory device of claim 8 , wherein the control logic being configured to cause the memory device to program the first memory cells to the levels within the first plurality of levels using the first set of program pulses

Assignees

• Micron Technology Inc

Inventors

• Sarin Vishal
• Vahidimowlavi Allahyar

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C2211/5648

  Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant · CPC title