Storage device and a write method thereof

Patent metadata

Field	Value
Publication number	US-9336866-B2
Application number	US-201414188889-A
Country	US
Kind code	B2
Filing date	Feb 25, 2014
Priority date	Jul 1, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A write method of a storage device includes determining whether to perform a coarse program operation based on information about memory cells of a memory device, in response to a determination that the coarse program operation is to be performed, programming data in the memory device by performing the coarse program operation and a fine program operation, and in response to a determination that the coarse program operation is not to be performed, programming data in the memory device by performing the fine program operation.

First claim

What is claimed is:

1. A write method of a storage device, comprising:
determining whether to perform a coarse program operation based on information about memory cells of a memory device,
in response to a determination that the coarse program operation is to be performed, programming data in the memory device by performing the coarse program operation and a fine program operation, and
in response to a determination that the coarse program operation is not to be performed, programming data in the memory device by performing the fine program operation,
wherein a range of a threshold voltage distribution near an upper program state is narrower than a range of a threshold voltage distribution near a lower program stage in the coarse program operation.

2. The write method of claim 1 , wherein the information about memory cells of the memory device includes program/erase cycle information, wear-leveling information, or information indicating whether a memory cell is programmed.

3. The write method of claim 1 , wherein the determination is made by a memory controller.

4. The write method of claim 1 , wherein the data programmed in the coarse program operation is provided via a first signal line to a buffer area.

5. The write method of claim 4 , wherein the buffer area is included in the memory device, a memory controller, or is separate from the memory device and the memory controller.

6. The write method of claim 4 , wherein the data programmed in the fine program operation is provided via a second signal line to a memory area of the memory device.

7. The write method of claim 1 , wherein a memory controller provides the memory device with an instruction whether to perform the coarse program operation and the fine program operation, or perform only the fine program operation.

8. The write method of claim 1 , wherein the memory device is a nonvolatile memory.

9. The write method of claim 8 , wherein the nonvolatile memory has a three-dimensional vertical array structure.

10. The write method of claim 1 , wherein the determination is made in response to a write request.

11. The write method of claim 1 , wherein a number of program states in the coarse program operation is based on a program/erase cycle number.

12. A write method of a storage device, comprising:
receiving a write request at a memory controller;
determining, at the memory controller, whether to perform a coarse program operation based on information about memory cells corresponding to the write request;
wherein when the information about the memory cells is between an initial state and a first threshold, the coarse program operation is determined not to be performed; and
when the information about the memory cells is between the first threshold and a second threshold, the coarse program operation is determined to be performed and data is programmed in the memory cells by performing the coarse program operation and a fine program operation,
wherein the information about the memory cells indicates a program/erase cycle number of the memory cells.

13. The write method of claim 12 , wherein the program/erase cycle number of the first threshold is less than the program/erase cycle number of the second threshold.

14. The write method of claim 13 , wherein data corresponding to an upper program state is programmed during the coarse program operation and data corresponding to a lower program state is not programmed during the coarse program operation.

15. The write method of claim 14 , wherein when the information about the memory cells exceeds the second threshold, the coarse program operation is determined to be performed and data is programmed in the memory cells by performing the coarse program operation.

16. The write method of claim 15 , wherein the program/erase cycle number of the memory cells is greater than the second threshold when the information about the memory cells exceeds the second threshold.

17. The write method of claim 15 , wherein data corresponding to all program states is programmed during the coarse program operation performed when the program/erase cycle number of memory cells exceeds the second threshold.

18. The write method of claim 12 , wherein a range of a threshold voltage distribution near an upper program state is narrower than a range of a threshold voltage distribution near a lower program stage in the coarse program operation.

19. A write method of a storage device, comprising:
receiving a write request for an address at a memory controller;
determining, at the memory controller, a type of coarse program operation to be performed on a memory cell associated with the address, wherein the type of coarse program operation is based on an expected time of start of a fine program operation after execution of the coarse program operation; and
outputting, from the memory controller to a memory device, an instruction to perform the determined type of coarse program operation.

20. The write method of claim 19 , wherein threshold voltage distributions in a first type coarse program operation are narrow when the expected time is short and threshold voltage distributions in a second type coarse program operation are wide when the expected time is long.

21. A write method of a storage device, comprising:
determining a type of coarse program operation to be performed based on information about memory cells of a memory device; and
in response to determining the type of coarse program operation to be performed, programming data in the memory device by performing the determined type of coarse program operation and a fine program operation,
wherein an increment of a voltage level of a program pulse in the coarse program operation is reduced.

22. The write method of claim 21 , wherein a number of program states formed in the coarse program operation increases as a program/erase cycle increases.

23. The write method of claim 21 , wherein a range of a threshold voltage distribution near a lower program state is narrower than a range of a threshold voltage distribution near an upper program state in the coarse program operation.

24. The write method of claim 21 , wherein program states of the coarse program operation are divided into a plurality of groups.

25. The write method of claim 24 , wherein the program states are grouped according to ranges of their threshold voltage distributions.

26. A write method of a storage device, comprising:
determining a type of coarse program operation to be performed based on information about memory cells of a memory device; and
in response to determining the type of coarse program operation to be performed, programming data in the memory device by performing the determined type of coarse program operation and a fine program operation,
wherein a duration between program pulses in the coarse program operation is different.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kwak Donghun
• Shim Dongkyo
• Park Kitae
• Park Hyun-Wook

Classifications

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title