Smart skip verify mode for programming a memory device

Patent metadata

Field	Value
Publication number	US-10014063-B2
Application number	US-201514928853-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Oct 30, 2015
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.

First claim

We claim:

1. An apparatus, comprising:
one set of memory cells connected to one word line;
a programming circuit configured to perform a programming operation for the one set of memory cells, wherein:
the one set of memory cells comprises memory cells assigned to represent a first data state among a plurality of data states and memory cells assigned to represent a second data state among the plurality of data states;
the programming operation comprising a plurality of program-verify iterations; and
in each program-verify iteration, the programming circuit performs programming for the one word line after which the programming circuit applies a verification signal to the one word line;

a counting circuit configured to obtain a count of one or more memory cells which pass a verify test for the first data state, the programming circuit configured to perform a number of program-verify iterations in which a verify test for the second data state is skipped, then perform a program-verify iteration in which the verify test for the second data state is performed for the memory cells assigned to represent the second data state, wherein the number is one or more and is a function of the count.

2. The apparatus of claim 1 , wherein:
the determination circuit configured to determine the number of program-verify iterations to skip in response to a determination that the count exceeds a bit ignore level.

3. The apparatus of claim 1 , wherein:
the counting circuit configured to obtain the count as a count of memory cells having a sensed threshold voltage above a verify voltage for the first data state.

4. The apparatus of claim 1 , wherein:
the verify test for the second data state is a first verify test for the second data state in the programming operation.

5. The apparatus of claim 1 , wherein:
the memory cells which pass the verify test of the first data state comprise some of the memory cells assigned to represent the first data state and some of the memory cells assigned to represent the second data state.

6. The apparatus of claim 1 , wherein:
the one set of memory cells comprises memory cells assigned to represent a third data state among the plurality of data states; and
the determination circuit configured to determine, based on the count, a program-verify iteration in which to cause the counting circuit to begin obtaining an additional count of memory cells which pass the verify test for the second data state, and to determine, when the additional count exceeds a respective threshold, and based on an amount by which the additional count exceeds the respective threshold, a program-verify iteration in which to perform a verify test for the third data state for the memory cells assigned to represent the third data state.

7. The apparatus of claim 6 , wherein:
the memory cells which pass the verify test of the second data state comprise some of the memory cells assigned to represent the third data state.

8. The apparatus of claim 4 , wherein:
the one set of memory cells is among a plurality of memory cells formed along tapered memory holes in a stack of alternating conductive and dielectric layers;
the one set of memory cells is at a particular height in the stack;
another set of memory cells connected to the one word line are at the particular height;
the another set of memory cells comprises memory cells assigned to represent the second data state; and
a program-verify iteration of a first verify test in a programming operation for the another set of memory cells is based on a program-verify iteration of the first verify test in the programming operation for the one set of memory cells.

9. The apparatus of claim 4 , wherein:
the one set of memory cells is among a plurality of memory cells formed along tapered memory holes in a stack of alternating conductive and dielectric layers;
the one set of memory cells is at a particular height in the stack;
another set of memory cells connected to another word line is at another height in the stack;
the another set of memory cells comprises memory cells assigned to represent the second data state; and
a program-verify iteration of a first verify test in a programming operation for the another set of memory cells is based on a program-verify iteration of the first verify test in the programming operation for the one set of memory cells and based on the another height.

10. A method, comprising:
performing initial program-verify iterations in a programming operation for a set of memory cells, the memory cells comprise memory cells assigned to a first data state among a plurality of data states and memory cells assigned to second data state among the plurality of data states;
during the initial program-verify iterations, obtaining a count of memory cells which pass a verify test of the first data state and determining that the count exceeds a threshold; and
in response to the obtaining the count and the determining that the count exceeds the threshold, determining a number of additional program-verify iterations of the programming operation to perform without performing a verify test of the second data state, before performing a program-verify iteration in which the memory cells assigned to the second data state are subject to the verify test of the second data state, the number is one or more program-verify iterations and is determined by accessing data which identifies different values of the number of additional program-verify iterations of the programming operation to perform without subjecting the memory cells assigned to the second data state to the verify test of the second data state, based on different values of the count.

11. The method of claim 10 , wherein:
the second data state has a verify voltage which is higher than a verify voltage of the first data state.

12. The method of claim 10 , wherein:
the memory cells which pass the verify test of the first data state comprise some of the memory cells assigned to represent the second data state.

13. An apparatus, comprising:
a set of memory cells; and
a control circuit, the control circuit configured to:
begin a programming operation for the set of memory cells to program the set of memory cells to a plurality of data states, the plurality of data states comprising one data state and a next higher data state, the programming operation comprising a plurality of program-verify iterations;
perform a verify test in the plurality of program-verify iterations for the one data state but not the next higher data state until a particular program-verify iteration in which a count of memory cells which pass the verify test for the one data state exceeds a threshold;
in response to the count exceeding the threshold, perform the verify test in the plurality of program-verify iterations for the one data state but not the next higher data state during a number of additional program-verify iterations, the number is one or more and is a decreasing function of the count; and
perform a first verify test in the plurality of program-verify iterations for the next higher data state after the number of additional program-verify iterations.

14. The apparatus of claim 13 , wherein:
the memory cells which pass the verify test of the one data state comprise memory cells assigned to represent the one data state and memory cells assigned to represent the next higher data state.

15. The method of claim 10 , further comprising:
classifying the count into a particular range of values among a plurality of ranges of values, wherein the number of additional program-verify iterations of the programming operatio

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Tseng Huai-Yuan
• Dutta Deepanshu
• Tseng Tai-Yuan
• Shah Grishma
• Masuduzzaman Muhammad

Classifications

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title