Shift register circuit and method of controlling the same, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-11244643-B2
Application number	US-201816179671-A
Country	US
Kind code	B2
Filing date	Nov 2, 2018
Priority date	Jan 10, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A shift register circuit includes a pull-up control sub-circuit, a pull-up sub-circuit and a shutdown auxiliary sub-circuit. The pull-up control sub-circuit is configured to transmit a voltage from the signal input terminal to the pull-up node under the control of the voltage from the signal input terminal. The shut-down auxiliary sub-circuit is configured to pull down a voltage of the pull-up node to a voltage of the discharge voltage terminal under the control of a voltage from the pull-up node. The pull-up sub-circuit is configured to transmit a voltage from the clock signal terminal to the first signal output terminal under the control of a voltage from the pull-up node. The first signal output terminal is configured to be connected to a gate line.

First claim

What is claimed is:

1. A shift register circuit, comprising:
a pull-up control sub-circuit connected to a signal input terminal and a pull-up node, wherein the pull-up control sub-circuit is configured to transmit a voltage from the signal input terminal to the pull-up node under control of the voltage from the signal input terminal;
a shutdown auxiliary sub-circuit connected to the pull-up node and a discharge voltage terminal, wherein the shutdown auxiliary sub-circuit is configured to pull down a voltage of the pull-up node to a voltage of the discharge voltage terminal under control of the voltage from the pull-up node in a shutdown control phase, the discharge voltage terminal is connected to a ground terminal;
a pull-up sub-circuit connected to a clock signal terminal, the pull-up node, a first signal output terminal and a second signal output terminal, wherein the pull-up sub-circuit is configured to transmit a voltage from the clock signal terminal to the first signal output terminal under control of a voltage from the pull-up node, and the first signal output terminal is configured to be connected to a gate line;
a first reset sub-circuit connected to a general reset signal terminal, the pull-up node and a first voltage terminal, wherein the first reset sub-circuit is configured to pull down a voltage of the pull-up node to a voltage of the first voltage terminal under control of a voltage from the general reset signal terminal;
a second reset sub-circuit connected to a first sub-reset signal terminal, a second sub-reset signal terminal, the pull-up node, the first signal output terminal and the first voltage terminal, wherein the second reset sub-circuit is configured to pull down a voltage of the first signal output terminal to a voltage of the first voltage terminal under control of a voltage from the first sub- reset signal terminal, and the second reset sub-circuit is further configured to pull down a voltage of the pull-up node to a voltage of the first voltage terminal under control of a voltage from the second sub-reset signal terminal;
a first pull-down control sub-circuit connected to a second voltage terminal, the signal input terminal, the pull-up node, a first pull-down node and the first voltage terminal, wherein the first pull-down control sub-circuit is configured to transmit a voltage from the second voltage terminal to the first pull-down node under control of the voltage from the second voltage terminal, and the first pull-down control sub-circuit is further configured to pull down a voltage of the first pull-down node to a voltage of the first voltage terminal under control from a voltage from the signal input terminal or a voltage from the pull-up node;
a second pull-down control sub-circuit connected to a third voltage terminal, the signal input terminal, the pull-up node, a second pull-down node and the first voltage terminal, wherein the second pull-down control sub-circuit is configured to transmit a voltage from the third voltage terminal to the second pull-down node under control of the voltage from the third voltage terminal, and the second pull-down control sub-circuit is further configured to pull down a voltage of the second pull-down node to a voltage of the first voltage terminal under control of a voltage from the signal input terminal or a voltage from the pull-up node;
a first pull-down sub-circuit connected to the pull-up node, the first signal output terminal, a first voltage terminal and the first pull-down node, wherein the first pull-down sub-circuit is configured to pull down voltages of the pull-up node and the first signal output terminal to a voltage of the first voltage terminal under control of a voltage from the first pull-down node;
a second pull-down sub-circuit connected to the pull-up node, the first signal output terminal, a first voltage terminal and the second pull-down node, wherein the second pull-down sub-circuit is configured to pull down voltages of the pull-up node and the first signal output terminal to a voltage of the first voltage terminal under control of a voltage from the second pull-down node;
wherein the pull-up control sub-circuit comprises a first transistor, a gate electrode and a first electrode of the first transistor are connected to the signal input terminal, and a second electrode of the first transistor is connected to the pull-up node;
wherein the second pull-down control sub-circuit comprises an eighth transistor, a ninth transistor and a tenth transistor;
a gate electrode and a first electrode of the eighth transistor are connected to the third voltage terminal, and a second electrode of the eighth transistor is connected to the second pull-down node;
a gate electrode of the ninth transistor is connected to the signal input terminal, a first electrode of the ninth transistor is connected to the second pull-down node, and a second electrode of the ninth transistor is connected to the first voltage terminal;
a gate electrode of the tenth transistor is connected to the pull-up node, a first electrode of the tenth transistor is connected to the second pull-down node, and a second electrode of the tenth transistor is connected to the first voltage terminal;
wherein the first reset sub-circuit comprises a second transistor, a gate electrode of the second transistor is connected to the general reset signal terminal, a first electrode of the second transistor is connected to the pull-up node, and a second electrode of the second transistor is connected to the first voltage terminal;
wherein the first pull-down control sub-circuit comprises a third transistor, a fourth transistor and a fifth transistor;
a gate electrode and a first electrode of the third transistor are connected to the second voltage terminal, and a second electrode of the third transistor is connected to the first pull-down node;
a gate electrode of the fourth transistor is connected to the signal input terminal, a first electrode of the fourth transistor is connected to the first pull-down node, and a second electrode of the fourth transistor is connected to the first voltage terminal;
a gate electrode of the fifth transistor is connected to the pull-up node, a first electrode of the fifth transistor is connected to the first pull-down node, and a second electrode of the fifth transistor is connected to the first voltage terminal;
wherein the second reset sub-circuit comprises a sixteenth transistor and a seventeenth transistor; a gate electrode of the sixteenth transistor is connected to the second sub-reset signal terminal, a first electrode of the sixteenth transistor is connected to the pull-up node, and a second electrode of the sixteenth transistor is connected to the first voltage terminal; and a gate electrode of the seventeenth transistor is connected to the first sub-reset signal terminal, a first electrode of the seventeenth transistor is connected to the first signal output terminal, and a second electrode of the seventeenth transistor is connected to the first voltage terminal;
wherein the pull-up sub-circuit comprises a driving transistor, a storage capacitor and a thirteenth transistor; a gate electrode of the driving transistor is connected to the pull-up node, a first electrode of the driving transistor is connected to the clock signal terminal, and a second electrode of the driving transistor is connected to the first signal output terminal; one end of the storage capacitor is connected to the gate electrode of the driving transistor, and another end of the storage capacitor is connected to the second electrode of the driving transistor; a gate electrode of the thirteenth transistor is connected to the pull-up node, a first electrode of the thirteenth transistor is connected to the clock signal terminal, and a second electrode of the thirteenth transistor is connected to the second signal output terminal;
wherein the first pu

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Wang Zixuan
• Chen Peng
• Yang Tong
• Qian Xianrui
• Chen Yuting
• Mu Suzhen
• Rui Zhou
• Xiong Xiong

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title