Shift register unit, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-9685134-B2
Application number	US-201514777587-A
Country	US
Kind code	B2
Filing date	Mar 19, 2015
Priority date	Nov 7, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

The present invention provides a shift register unit, a gate driving circuit and a display device, which belongs to the field of display technology. The shift register unit of the present invention comprises: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module.

First claim

What is claimed is:

1. A shift register unit, comprising: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module;
the input module being connected to a signal input end and a pull-up control node, for controlling electric potential of the pull-up control node based on a signal inputted by the signal input end, the pull-up control node being a connection point of the input module and the pull-up module;
the pull-up module being connected to the pull-up control node, a first clock signal port and a signal output end, for pulling up a signal outputted by the signal output end to be of high level based on the control of the electric potential of the pull-up control node and a clock signal inputted by the first clock signal port;
the pull-down control module being connected to a pull-down control node and a second clock signal port, for controlling a level of the pull-down control node based on a level of the second clock signal port, the pull-down control node being a connection point of the pull-down control module and the pull-down module;
the pull-down module being connected to the pull-down control node, the pull-up control node and a low level signal, for pulling down the pull-down control node to be a low level through the low level signal based on the electric potential of the pull-up control node;
the discharge module comprising a discharge capacitor, a first end of the discharge capacitor being connected to the pull-up module and the pull-up control node, a second end being connected to an output signal reset input end, for maintaining the electric potential of the pull-up control node under the control of a signal inputted by the output signal reset input end, the signal output end being discharged through the pull-up module;
the reset module being connected to a reset signal input end, the pull-up control node and the low level signal, for pulling down the level of the pull-up control node through a signal inputted by the reset signal input end,
wherein the discharge module further comprises a discharge device, the discharge device being connected to the signal output end, the low level signal and the discharge capacitor, for discharging the signal output end based on the electric potential of the discharge capacitor, and the discharge device comprises a seventh transistor, a first terminal of the seventh transistor is connected to the second terminal of the second transistor, the second end of the storage capacitor and the signal output end, a second terminal is connected to the low level signal, a control terminal is connected to the second end of the discharge capacitor.

2. The shift register unit according to claim 1 , wherein the input module comprises a first transistor, a first terminal of the first transistor is connected to its control terminal and the signal input end, a second terminal is connected to the pull-up control node.

3. The shift register unit according to claim 2 , wherein the pull-up module comprises a second transistor and a storage capacitor,
a first terminal of the second transistor is connected to the first clock signal port, a second terminal is connected to a second end of the storage capacitor and the signal output end, a control terminal is connected to the pull-up control node;
a first end of the storage capacitor is connected to the pull-up control node and the first end of the discharge capacitor.

4. The shift register unit according to claim 3 , wherein the pull-down control module comprises a third transistor and a fourth transistor,
a first terminal of the third transistor is connected to its control terminal and a second terminal of the fourth transistor, a second terminal is connected to a control terminal of the fourth transistor and the pull-down module, a control terminal is connected to the second clock signal port;
a first terminal of the fourth transistor is connected to the pull-down control node.

5. The shift register unit according to claim 4 , wherein the pull-down module comprises a fifth transistor and a sixth transistor,
a first terminal of the fifth transistor is connected to the second terminal of the third transistor and the control terminal of the fourth transistor, a second terminal is connected to the low level signal, a control terminal is connected to a control terminal of the sixth transistor;
a first terminal of the sixth transistor is connected to the pull-down control node, a second terminal is connected to a low level signal, the control terminal is connected to the pull-up control node.

6. The shift register unit according to claim 1 , wherein the reset module comprises an eighth transistor,
a first terminal of the eighth transistor is connected to the pull-up control node, a second terminal is connected to the low level signal, a control terminal is connected to the reset signal input end.

7. A shift register unit, comprising: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module;
the input module being connected to a signal input end and a pull-up control node, for controlling electric potential of the pull-up control node based on a signal inputted by the signal input end, the pull-up control node being a connection point of the input module and the pull-up module;
the pull-up module being connected to the pull-up control node, a first clock signal port and a signal output end, for pulling up a signal outputted by the signal output end to be of high level based on the control of the electric potential of the pull-up control node and a clock signal inputted by the first clock signal port;
the pull-down control module being connected to a pull-down control node and a second clock signal port, for controlling a level of the pull-down control node based on a level of the second clock signal port, the pull-down control node being a connection point of the pull-down control module and the pull-down module;
the pull-down module being connected to the pull-down control node, the pull-up control node and a low level signal, for pulling down the pull-down control node to be a low level through the low level signal based on the electric potential of the pull-up control node;
the discharge module comprising a discharge capacitor, a first end of the discharge capacitor being connected to the pull-up module and the pull-up control node, a second end being connected to an output signal reset input end, for maintaining the electric potential of the pull-up control node under the control of a signal inputted by the output signal reset input end, the signal output end being discharged through the pull-up module;
the reset module being connected to a reset signal input end, the pull-up control node and the low level signal, for pulling down the level of the pull-up control node through a signal inputted by the reset signal input end,
wherein the shift register unit further comprises a noise reduction module, the noise reduction module being connected to the low level signal, the pull-up control node and the pull-down control node, for pulling down the electric potential of the pull-up control node through the low level signal based on the electric potential of the pull-down control node, so as to remove noise of the shift register unit, and the noise reduction module comprises a ninth transistor and a tenth transistor,
a first terminal of the ninth transistor is connected to the pull-up control node, a second terminal is connected to the low level signal, a control terminal is connected to the pull-down control node;
a first terminal of the tenth transistor is connected to the signal output end, a second terminal is connected to the low level signal, a control terminal is conn

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Yuanbo
• Han Seungwoo
• Im Yunsik

Classifications

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title