Shift register units and driving methods thereof, gate driving circuits and display devices with transistors having extended lifetime

Patent metadata

Field	Value
Publication number	US-10269290-B2
Application number	US-201715680416-A
Country	US
Kind code	B2
Filing date	Aug 18, 2017
Priority date	Jan 3, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

First claim

What is claimed is:

1. A shift register unit, comprising: an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits, wherein
the input circuit is connected to the plurality of output circuits and configured to receive an input signal and output the received input signal to the plurality of output circuits;
the reset circuit is configured to reset the plurality of output circuits according to a reset signal;
the plurality of output circuits are configured to output output signals based on the input signal and clock signals;
the plurality of pull-down circuits are connected to output terminals of the plurality of output circuits and are configured to pull down voltages at the output terminals of the plurality of output circuits;
the plurality of pull-down control circuits are connected to the plurality of pull-down circuits and are configured to control the plurality of pull-down circuits;
wherein, the shift register unit is configured so that,
during a first time period, all of the output signals of the plurality of output circuits are valid, and
during a second time period, at least one of the output signals of the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and a state of at least one of the output signals of the plurality of output circuits during the first sub-period is opposite to a state thereof during the second sub-period,

wherein a time period of each of frames comprises a first time period and a second time period;
the frames comprises a first frame and a second frame;
the plurality of output circuits comprise a first output circuit and a second output circuit;
wherein, during the second time period of the first frame, the output signal of the first output circuit is invalid, and the output signal of the second output circuit is valid;
during the second time period of the second frame, the output signal of the second output circuit is invalid, and the output signal of the first output circuit is valid.

2. The shift register unit of claim 1 , wherein,
the plurality of pull-down circuits comprise a first pull-down circuit and a second pull-down circuit; the plurality of pull-down control circuits comprise a first pull-down control circuit and a second pull-down control circuit;
a connection point connecting the input circuit with the plurality of output circuits is a pull-up point; a connection point connecting the first pull-down control circuit with the first pull-down circuit is a first pull-down point; a connection point connecting the second pull-down control circuit with the second pull-down circuit is a second pull-down point;
the first output circuit is connected to the pull-up point and a first clock terminal, and the first output circuit provides a first output terminal;
the first pull-down circuit is connected to the first pull-down point, a first voltage terminal, a fifth voltage terminal, the pull-up point, and the first output terminal;
the first pull-down control circuit is connected to the input signal terminal, the pull-up point, a third voltage terminal, the first output terminal, the fifth voltage terminal, and the first pull-down point;
the second output circuit is connected to the pull-up point and a second clock terminal, and the second output circuit provides a second output terminal;
the second pull-down circuit is connected to the second pull-down point, the first voltage terminal, the fifth voltage terminal, the pull-up point, and the second output terminal; and
the second pull-down control circuit is connected to the input signal terminal, the pull-up point, a fourth voltage terminal, the second output terminal, the fifth voltage terminal, and the second pull-down point.

3. The shift register unit of claim 2 , wherein,
the input circuit comprises a first transistor, which has a control terminal and a first terminal both connected to the input signal terminal, and a second terminal connected to the pull-up point;
the reset circuit comprises a second transistor, which has a control terminal connected to a reset signal terminal, a first terminal connected to the fifth voltage terminal, and a second terminal connected to the pull-up point.

4. The shift register unit of claim 2 , wherein
the first output circuit comprises a third transistor and a first capacitor, wherein the third transistor has a control terminal connected to the pull-up point, s first terminal connected to the first clock terminal, and a second terminal connected to one of the plurality of pull-down circuits, the first capacitor being connected between the control terminal and the second terminal of the third transistor, and a connection point connecting the second terminal of the third transistor with the first capacitor being the first output terminal;
the second output circuit comprises a fourth transistor and a second capacitor, wherein the fourth transistor has a control terminal connected to the pull-up point, a first terminal connected to the second clock terminal, and a second terminal connected to one of the plurality of pull-down circuits, the second capacitor being connected between the control terminal and the second terminal of the fourth transistor, and a connection point connecting the second terminal of the fourth transistor with the second capacitor being the second output terminal.

5. The shift register unit of claim 2 , further comprising: a cascade circuit, a cascade pull-down circuit, and a cascade pull-down control circuit,
wherein the cascade circuit is configured to output a cascade signal that is used as at least one of an input signal and a reset signal of another shift register unit; the cascade pull-down circuit is connected to an output terminal of the cascade circuit, and is configured to pull-down the output terminal of the cascade circuit; the cascade pull-down control circuit is connected to the cascade pull-down circuit, and is configured to control the cascade pull-down circuit;
the cascade circuit comprises a fifth transistor, wherein the fifth transistor has a control terminal connected to the pull-up point, a first terminal connected to a third clock terminal, and a second terminal connected to a third output terminal and also to the cascade pull-down circuit;
the cascade pull-down circuit comprises a sixth transistor and a seventh transistor, wherein the sixth transistor has a control terminal connected to the cascade pull-down control circuit, a first terminal connected to the fifth voltage terminal, and a second terminal connected to the third output terminal; the seventh transistor has a control terminal connected to the cascade pull-down control circuit, a first terminal connected to the fifth voltage terminal, and a second terminal connected to the third output terminal;
the cascade pull-down control circuit multiplexes the plurality of pull-down control circuits, the control terminal of the sixth transistor being connected to a first pull-down control circuit of the plurality of pull-down control circuits, the control terminal of the seventh transistor being connected to a second pull-down control circuit of the plurality of pull-down control circuits.

6. The shift register unit of claim 2 , wherein
the first pull-down circuit comprises an eighth transistor and a ninth transistor, wherein the eighth transistor has a control terminal connected to the first pull-down point, a first terminal connected to the fifth voltage terminal, and a second terminal connected to the pull-up point; the ninth transistor has a control terminal connected to the first pull-down point, a first terminal connected to the first voltage terminal, and a second terminal connected to the

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shang Guangliang
• Han Mingfu
• Zheng Haoliang
• Woo Han-Seung-
• Sik Im-Yun-
• Lv Jing
• Huang Yinglong
• Mok Jun-Jung-
• Dong Xue
• Wang Zhichong
• Yao Xing
• Yuan Lijun
• Jin Zhihe

Classifications

• G09G2330/02

  Details of power systems and of start or stop of display operation · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title