Semiconductor device, display device, and electronic device

Patent metadata

Field	Value
Publication number	US-10032428-B2
Application number	US-201615223659-A
Country	US
Kind code	B2
Filing date	Jul 29, 2016
Priority date	Nov 28, 2012
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

To prevent an influence of normally-on characteristics of the transistor which a clock signal is input to a terminal of, a wiring to which a first low power supply potential is applied and a wiring to which a second low power supply potential lower than the first low power supply potential is applied are electrically connected to a gate electrode of the transistor. A semiconductor device including the transistor can operate stably.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first input terminal to which a start pulse signal is input;
a second input terminal to which a clock signal is input;
a third input terminal to which a reset signal is input;
a fourth input terminal to which an inverted start pulse signal is input;
a first output terminal from which a pulse signal is output;
a second output terminal from which a pulse signal is output;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor; and
a capacitor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first input terminal,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor, one electrode of the capacitor, and one of a source electrode and a drain electrode of the fifth transistor,
wherein a gate electrode of the first transistor is electrically connected to the one of the source electrode and the drain electrode of the first transistor,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the second input terminal,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor, a gate electrode of the eighth transistor, and the first output terminal,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,
wherein a gate electrode of the third transistor is electrically connected to the third input terminal,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a wiring to which a first low power supply potential is applied,
wherein a gate electrode of the fourth transistor is electrically connected to the fourth input terminal,
wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor,
wherein a gate electrode of the fifth transistor is electrically connected to the third input terminal,
wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to a wiring to which a second low power supply potential lower than the first low power supply potential is applied,
wherein a gate electrode of the sixth transistor is electrically connected to the fourth input terminal,
wherein one of a source electrode and a drain electrode of the seventh transistor is electrically connected to a wiring to which a first high power supply potential is applied,
wherein the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to one of a source electrode and a drain electrode of the eighth transistor and a second output circuit,
wherein a gate electrode of the seventh transistor is electrically connected to one of a source electrode and a drain electrode of the seventh transistor,
wherein the other of the source electrode and the drain electrode of the eighth transistor is electrically connected to a wiring to which the second low power supply potential is applied,
wherein the other electrode of the capacitor is electrically connected to a first output circuit,
wherein the start pulse signal includes the first low power supply potential and a high power supply potential, and
wherein the second low power supply potential is applied to the gate electrode of the second transistor through the fifth transistor and the sixth transistor, when the start pulse signal is the first low power supply potential.

2. The semiconductor device according to claim 1 , wherein a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor comprises an oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the first high power supply potential is lower than the second high power supply potential.

4. A display device comprising:
the semiconductor device according to claim 1 ; and
a pixel circuit where data writing and storing of a data signal are controlled by the semiconductor device.

5. An electronic device comprising the display device according to claim 4 .

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Miyake Hiroyuki
• Matsubayashi Daisuke

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3696 Primary

  Generation of voltages supplied to electrode drivers · CPC title

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title