Shift register, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-2016307641-A1
Application number	US-201615085117-A
Country	US
Kind code	A1
Filing date	Mar 30, 2016
Priority date	Apr 14, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

The present invention provides a shift register, a gate driving circuit and a display device. The shift register comprises an input unit, an output pull-up unit, a reset unit and an output maintaining unit, the input unit is connected with a signal input terminal, the reset unit and a pull-up control node, and the pull-up control node is a connection node between the input unit and the output pull-up unit; the output pull-up unit is connected with a first signal output terminal, a second signal output terminal, a first clock signal input terminal, the reset unit and the pull-up control node; the reset unit is connected with a reset signal input terminal, a low voltage power supply terminal, the input unit and the output pull-up unit; the output maintaining unit is connected with the first clock signal input terminal, the first signal output terminal and a control signal input terminal.

First claim

1 . A shift register, comprising an input unit, an output pull-up unit, a reset unit and an output maintaining unit, wherein,
the input unit is connected with a signal input terminal, the reset unit and a pull-up control node, and is configured to control potential of the pull-up control node in accordance with a signal inputted from the signal input terminal, the pull-up control node is a connection node between the input unit and the output pull-up unit; the output pull-up unit is connected with a first signal output terminal, a second signal output terminal, a first clock signal input terminal, the reset unit and the pull-up control node, and is configured to control output of the first signal output terminal in accordance with potential of the pull-up control node and signal inputted from the first clock signal input terminal; the reset unit is connected with a reset signal input terminal, a low voltage power supply terminal, the input unit and the output pull-up unit, and is configured to reset signals outputted by the input unit and the output pull-up unit in accordance with signal inputted from the reset signal input terminal; the output maintaining unit is connected with the first clock signal input terminal, the first signal output terminal and a control signal input terminal, and is configured to maintain output of the first signal output terminal in accordance with signals inputted from the control signal input terminal and the first clock signal input terminal.

2 . The shift register of claim 1 , further comprises a pull-down control unit and a pull-down unit,
the pull-down control unit is connected with a second clock signal input terminal and a pull-down node, and is configured to control potential of the pull-down node in accordance with signal inputted from the second clock signal input terminal, the pull-down node is a connection node between the pull-down control unit and the pull-down unit; the pull-down unit is connected with the signal input terminal, the first clock signal input terminal, the pull-down node, the pull-up control node and the low voltage power supply terminal, and is configured to pull down potential of the pull-down node in accordance with potential of the pull-up control node, signal inputted from the signal input terminal and signal inputted from the first clock signal input terminal.

3 . The shift register of claim 2 , wherein the pull-down control unit comprises a fifth transistor, the pull-down unit comprises a sixth transistor, a seventh transistor and a ninth transistor,
a first electrode of the fifth transistor is connected with the second clock signal input terminal, a second electrode of the fifth transistor is connected with the pull-down node, and a control electrode of the fifth transistor is also connected with the second clock signal input terminal; a first electrode of the sixth transistor is connected with the pull-down node, a second electrode of the sixth transistor is connected the low voltage power supply terminal, and a control electrode of the sixth transistor is connected with the pull-up control node; a first electrode of the seventh transistor is connected with the pull-down node, a second electrode of the seventh transistor is connected with the low voltage power supply terminal, and a control electrode of the seventh transistor is connected with the signal input terminal; a first electrode of the ninth transistor is connected with the pull-down node, a second electrode of the ninth transistor is connected with the low voltage power supply terminal, and a control electrode of the ninth transistor is connected with the first clock signal input terminal.

4 . The shift register of claim 1 , wherein the input unit comprises a first transistor,
a first electrode of the first transistor is connected with the signal input terminal, a second electrode of the first transistor is connected with the pull-up control node, and a control electrode of the first transistor is also connected with the signal input terminal.

5 . The shift register of claim 2 , wherein the input unit comprises a first transistor,
a first electrode of the first transistor is connected with the signal input terminal, a second electrode of the first transistor is connected with the pull-up control node, and a control electrode of the first transistor is also connected with the signal input terminal.

6 . The shift register of claim 1 , wherein the output pull-up unit comprises a third transistor, an eleventh transistor and a storage capacitor,
a first electrode of the third transistor is connected with the first clock signal input terminal, a second electrode of the third transistor is connected with the first signal output terminal, and a control electrode of the third transistor is connected with the pull-up control node; a first electrode of the eleventh transistor is connected with the first clock signal input terminal, a second electrode of the eleventh transistor is connected with the second signal output terminal, and a control electrode of the eleventh transistor is connected with the pull-up control node; a first terminal of the storage capacitor is connected with the pull-up control node, and a second terminal of the storage capacitor is connected with the first signal output terminal.

7 . The shift register of claim 2 , wherein the output pull-up unit comprises a third transistor, an eleventh transistor and a storage capacitor,
a first electrode of the third transistor is connected with the first clock signal input terminal, a second electrode of the third transistor is connected with the first signal output terminal, and a control electrode of the third transistor is connected with the pull-up control node; a first electrode of the eleventh transistor is connected with the first clock signal input terminal, a second electrode of the eleventh transistor is connected with the second signal output terminal, and a control electrode of the eleventh transistor is connected with the pull-up control node; a first terminal of the storage capacitor is connected with the pull-up control node, and a second terminal of the storage capacitor is connected with the first signal output terminal.

8 . The shift register of claim 2 , wherein the output maintaining unit comprises a fifteenth transistor,
a first electrode of the fifteenth transistor is connected with the first clock signal input terminal, a second electrode of the fifteenth transistor is connected with the first signal output terminal, and a control electrode of the fifteenth transistor is connected with the control signal input terminal.

9 . The shift register of claim 8 , wherein the output maintaining unit further comprises a sixteenth transistor,
a first electrode of the sixteen transistor is connected with the first clock signal input terminal, a second electrode of the sixteenth transistor is connected with the pull-up control node, and a control electrode of the sixteenth transistor is connected with the control signal input terminal.

10 . The shift register of claim 9 , wherein the output maintaining unit further comprises a seventeenth transistor,
a first electrode of the seventeenth transistor is connected with the first clock signal input terminal, a second electrode of the seventeenth transistor is connected with the pull-down node, and a control electrode of the seventeenth transistor is connected with the control signal input terminal.

11 . The shift register of claim 1 , wherein the reset unit comprises an input reset module and an output reset module,
the input reset module is connected with the reset signal input terminal, the low voltage power supply terminal and the input

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zheng Haoliang
• Shang Guangliang

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title