Semiconductor device and semiconductor package including the same

Patent metadata

Field	Value
Publication number	US-11239171-B2
Application number	US-202016922163-A
Country	US
Kind code	B2
Filing date	Jul 7, 2020
Priority date	Nov 7, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a first surface and a second surface opposing each other;
a plurality of semiconductor elements disposed on the first surface in a device region,
wherein the second surface is divided into a first region overlapping the device region, and a second region surrounding the first region;
an insulating protective layer disposed on the second surface of the semiconductor substrate,
wherein the insulating protective layer comprises an edge pattern positioned in the second region,
wherein the edge pattern comprises a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate; and
a connection pad disposed on the center portion of the insulating protective layer and electrically connected to the semiconductor elements.

2. The semiconductor device of claim 1 , wherein the edge pattern is disposed along an edge of the second surface.

3. The semiconductor device of claim 1 , wherein the edge pattern surrounds the first region and further comprises a convex portion disposed along an edge of the second surface.

4. The semiconductor device of claim 1 , wherein the open region surrounds the first region, and the edge pattern further comprises a plurality of convex structures arranged in the open region and comprising a same material as the insulating protective layer.

5. The semiconductor device of claim 4 , wherein the plurality of convex structures is arranged in a plurality of rows to surround the first region.

6. The semiconductor device of claim 1 , wherein the edge pattern comprises a plurality of concave patterns formed in the insulating protective layer, and each of the plurality of concave patterns is provided as the thinner portion and/or the open region.

7. The semiconductor device of claim 6 , wherein the plurality of concave patterns is arranged in a plurality of rows to surround the first region.

8. The semiconductor device of claim 1 , wherein the edge pattern comprises an extended portion extending into the first region, and the extended portion is spaced apart from the connection pad.

9. The semiconductor device of claim 1 , further comprising:
a through-electrode penetrating the semiconductor substrate and electrically connecting the semiconductor elements and the connection pad.

10. The semiconductor device of claim 9 , further comprising:
a first wiring structure disposed on the first surface of the semiconductor substrate and electrically connected to the device region.

11. The semiconductor device of claim 10 , further comprising:
a second wiring structure disposed between the insulating protective layer and the connection pad, and electrically connecting the through-electrode and the connection pad.

12. The semiconductor device of claim 11 , wherein the second wiring structure comprises a metal wiring electrically connecting the through-electrode and the connection pad, and a dielectric layer disposed on the insulating protective layer,
wherein the dielectric layer covers the metal wiring and fills the thinner portion and/or the open region of the edge pattern.

13. The semiconductor device of claim 1 , wherein the edge pattern comprises at least a portion of a scribe lane and an alignment key.

14. A semiconductor package, comprising:
a first semiconductor device having a lower surface on which a lower connection pad is disposed and an upper surface on which an upper connection pad is disposed, and comprising a through-electrode electrically connecting the lower connection pad and the upper connection pad; and
a second semiconductor device stacked on the upper surface of the first semiconductor device, and electrically connected to the upper connection pad,
wherein the first semiconductor device comprises:
a semiconductor substrate having a first surface and a second surface facing the lower surface and the upper surface of the first semiconductor device, respectively,
wherein the first surface comprises a device region,
wherein the second surface is divided into a first region overlapping the device region, and a second region surrounding the first region;
a first wiring structure disposed on the first surface of the semiconductor substrate and electrically connecting the device region and the lower connection pad; and
an insulating protective layer disposed on the second surface of the semiconductor substrate,
wherein the insulating protective layer comprises an edge pattern positioned in the second region,
wherein the edge pattern comprises a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate.

15. The semiconductor package of claim 14 , further comprising:
a second wiring structure comprising a dielectric layer disposed between the insulating protective layer and the upper connection pad, and a metal wiring disposed on the dielectric layer and electrically connecting the upper connection pad and the through-electrode.

16. The semiconductor package of claim 15 , wherein the dielectric layer comprises a material different from that of the insulating protective layer, and fills at least a portion of the edge pattern.

17. The semiconductor package of claim 14 , wherein the edge pattern has a portion disposed in the first region adjacent to the second region.

18. The semiconductor package of claim 14 , wherein the first semiconductor device comprises a plurality of vertically stacked semiconductor devices, and the second semiconductor device is connected to an uppermost connection pad of an uppermost semiconductor device of the plurality of first semiconductor devices.

19. A semiconductor package, comprising:
a package substrate having a circuit pattern;
a first semiconductor device disposed on the package substrate, having a lower surface on which a lower connection pad connected to the circuit pattern is disposed and an upper surface on which an upper connection pad is disposed, and comprising a through-electrode electrically connecting the lower connection pad and the upper connection pad; and
a second semiconductor device stacked on the upper surface of the first semiconductor device, and electrically connected to the upper connection pad,
wherein the first semiconductor device comprises:
a semiconductor substrate having a first surface and a second surface facing the lower surface and the upper surface of the first semiconductor device, respectively,
wherein the first surface comprises a device region,
wherein the second surface is divided into a first region overlapping the device region, and a second region surrounding the first region;
a first wiring structure disposed on the first surface of the semiconductor substrate and electrically connecting the device region and the lower connection pad;
an insulating protective layer disposed on the second surface of the semiconductor substrate,
wherein the insulating protective layer comprises an edge pattern positioned in the second region,
wherein the edge pattern comprises a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate; and
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Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Yeongkwon
• Lee Jaeeun
• Heo Junyeong

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title