Topside-cooled semiconductor package with molded standoff

Patent metadata

Field	Value
Publication number	US-11239127-B2
Application number	US-202016906617-A
Country	US
Kind code	B2
Filing date	Jun 19, 2020
Priority date	Jun 19, 2020
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

First claim

What is claimed is:

1. A topside-cooled semiconductor package, comprising:
a topside-cooling component;
a die pad;
a semiconductor situated between the die pad and the topside-cooling component;
a plurality of leads,
wherein a first set of leads, of the plurality of leads, and the die pad are formed from a same piece of conductive material,
wherein a bottom plane of the first set of leads is offset from a bottom surface of the die pad, and

wherein a second set of leads, of the plurality of leads, are connected to the topside-cooling component,
wherein a bottom plane of the second set of leads is coplanar to the bottom plane of the first set of leads within an electrical contact plane of the plurality of leads; and

a mold structure that is formed to enclose the semiconductor, the die pad, and a portion of the topside-cooling component within the mold structure,
wherein the mold structure includes a molded standoff that is beneath the die pad and extends downward from the electrical contact plane.

2. The topside-cooled semiconductor package of claim 1 , further comprising a trace that connects an electrode of the semiconductor to at least one of the second set of leads.

3. The topside-cooled semiconductor package of claim 1 , wherein the bottom plane of the first set of leads is offset from the bottom surface of the die pad by at least half of a thickness of the piece of conductive material, prior to the first set of leads and the die pad being formed.

4. The topside-cooled semiconductor package of claim 1 , wherein the topside-cooling component is a same type of material as at least one of:
the piece of conductive material, or
the second set of leads.

5. The topside-cooled semiconductor package of claim 1 , wherein the molded standoff includes a plurality of supports and a plurality of indentations between the supports.

6. The topside-cooled semiconductor package of claim 1 , wherein a thickness of the molded standoff is within a threshold range of half of a distance between the bottom surface of the die pad and the bottom surface of the molded standoff.

7. The topside-cooled semiconductor package of claim 1 , wherein a width of the molded standoff is less than a distance between inner edges of the first set of leads and inner edges of the second set of leads.

8. The topside-cooled semiconductor package of claim 1 , wherein a bottom surface of the molded standoff is parallel to at least one of:
the bottom surface of the die pad, or
a top surface of the topside-cooling component.

9. The topside-cooled semiconductor package of claim 1 , wherein the mold structure is formed from a mold compound.

10. The topside-cooled semiconductor package of claim 1 , wherein the semiconductor includes at least one of:
a half bridge, or
a transistor.

11. A molded semiconductor package arrangement, comprising:
a die pad configured to support a semiconductor;
a first set of leads,
wherein the first set of leads and the die pad are formed from a same piece of conductive material,
wherein an electrical contact plane of the set of leads is offset from a bottom surface of the die pad; a second set of leads connected to a topside-cooling component,
wherein a bottom plane of the second set of leads is coplanar to the bottom plane of the first set of leads within an electrical contact plane of the molded semiconductor package; and

a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure,
wherein the mold structure includes a molded standoff that is beneath the die pad, and
wherein a bottom surface of the molded standoff extends below the electrical contact plane of the first set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

12. The molded semiconductor package arrangement of claim 11 , further comprising:
a topside-cooling component that is to facilitate topside cooling associated with the semiconductor,
wherein the semiconductor is positioned between the topside-cooling component and the die pad.

13. The molded semiconductor package arrangement of claim 12 , wherein a top surface of the mold structure is coplanar to a top surface of the topside-cooling component.

14. The molded semiconductor package of claim 11 , wherein the thickness of the molded standoff is greater than or equal to half a thickness of the piece of conductive material.

15. The molded semiconductor package arrangement of claim 11 , wherein the molded standoff includes an indentation that is to form an enclosure between a surface of the indentation and a printed circuit board when the molded semiconductor package is installed on the printed circuit board,
wherein the enclosure reduces heat dissipation from the die pad to the printed circuit board.

16. A method of manufacturing a molded semiconductor package, the method comprising:
forming a first conductive portion of the molded semiconductor package,
wherein the first conductive portion is formed to include a die pad and a first set of leads,
wherein a bottom plane of the first set of leads is offset from a bottom surface of the die pad;

forming a second conductive portion of the molded semiconductor package,
wherein the second conductive portion is formed to include a topside-cooling component and a second set of leads connected to the topside-cooling component;

forming a semiconductor assembly by placing a semiconductor of the molded semiconductor package between the die pad and the topside-cooling component,
wherein the semiconductor assembly is formed so that the bottom plane of the first set of leads is coplanar to a bottom plane of the second set of leads to form an electrical contact plane of the molded semiconductor package; and

forming a mold structure of the molded semiconductor package,
wherein the mold structure is formed to enclose the die pad and the semiconductor within the mold structure,
wherein the mold structure is formed to have a top surface of the mold structure that is coplanar to a top surface of the topside-cooling component, and
wherein the mold structure is formed to have a molded standoff that has a bottom surface that is beneath the die pad and extends below the electrical contact plane.

17. The method of claim 16 , wherein forming the first conductive portion of the molded semiconductor package comprises:
punching a workpiece from a sheet of conductive material; and
stamping the die pad or the first set of leads to offset the die pad from the first set of leads.

18. The method of claim 16 , wherein forming the mold structure of the molded semiconductor package comprises:
placing the semiconductor assembly into a mold that is shaped to form the mold structure; and
supplying a mold compound, in a fluid state, to the mold,
wherein the mold includes a mold cavity that is configured to improve a flow of the mold compound, in the fluid state, into the mold and form the molded standoff; and

enabling the mold compound to transition from the fluid state to a solid state to form the mold structure.

19. The method of claim 16 , wherein the mold structure is formed to expose portions of the first set of leads and portions of the second set of leads at the electrical contact plane.

20. The method of claim 16 , the method comprises:
prior to forming the mold structure, forming a mold that is shaped to form the mold structure,
wherein the mold is formed to include a mold cavity that is shaped to form the molded standoff.

Assignees

• Infineon Technologies Ag

Inventors

• Myers Edward
• Chen Liu
• Chong Chee Chiew
• Lim Wee Aun Jason
• Tay Wee Boon

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/551

  Materials of bond wires · CPC title

• H10W74/016

  using moulds · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title