Semiconductor package with top side cooling heat sink thermal pathway

US9812373B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9812373-B2
Application numberUS-201514960804-A
CountryUS
Kind codeB2
Filing dateDec 7, 2015
Priority dateDec 8, 2014
Publication dateNov 7, 2017
Grant dateNov 7, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic module includes a semiconductor package including a semiconductor chip and an electrically insulating encapsulation body encapsulating the semiconductor chip, the encapsulation body completely covering a second main face and four side faces of the semiconductor chip, wherein a first main face of the semiconductor chip that is opposite the first main face is exposed from the encapsulation body, a heat spreader attached to the semiconductor package, the heat spreader completely covering the first main face of the semiconductor chip, and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package. The electrically insulating layer is completely separated from the semiconductor chip.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic module, comprising: a semiconductor package comprising a semiconductor chip and an electrically insulating encapsulation body encapsulating the semiconductor chip, the encapsulation body completely covering a second main face and four side faces of the semiconductor chip, wherein a first main face of the semiconductor chip that is opposite the second main face is exposed from the encapsulation body; a heat spreader attached to the semiconductor package, the heat spreader completely covering the first main face of the semiconductor chip; and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package, wherein the electrically insulating layer is completely separated from the semiconductor chip. 2. The electronic module of claim 1 , wherein the electronic module is a Surface Mounted Device (SMD). 3. The electronic module of claim 1 , wherein a second main face of the semiconductor package comprises electrical contact elements for electrically contacting a semiconductor chip of the semiconductor package from outside of the semiconductor package, and wherein the heat spreader is arranged on a first main face of the semiconductor package, the first main face being opposite the second main face. 4. The electronic module of claim 1 , wherein the heat spreader is electrically coupled to the semiconductor chip of the semiconductor package. 5. The electronic module of claim 1 , wherein the semiconductor chip is a semiconductor power chip. 6. The electronic module of claim 1 , wherein a thermal interface material is arranged between the semiconductor chip of the semiconductor package and the heat spreader, and wherein the thermal interface material comprises one or more of a solder, a thermal grease, a silver paste and a conductive adhesive. 7. The electronic module of claim 1 , wherein the electrically insulating layer electrically insulates the heat spreader against the outside world. 8. The electronic module of claim 1 , wherein the heat spreader laterally projects beyond a footprint of the semiconductor package. 9. The electronic module of claim 1 , further comprising a heat sink arranged on a first main surface of the heat spreader and electrically insulated from the heat spreader by the electrically insulating layer. 10. The electronic module of claim 1 , wherein the heat spreader comprises one or more of copper and aluminum. 11. The electronic module of claim 5 , wherein a drain contact or a collector contact of the semiconductor power chip faces the heat spreader. 12. The electronic module of claim 5 , wherein a source contact or an emitter contact of the semiconductor power chip faces the heat spreader. 13. The electronic module of claim 6 , wherein a chip carrier or a contact clip is arranged between the semiconductor chip and the thermal interface material. 14. A heat spreader, comprising: a metal sheet or metal plate, an electrically insulating layer arranged over the metal sheet or metal plate, wherein the metal sheet or metal plate has a thickness in the range of 0.1 mm-1 mm, and wherein the electrically insulating layer completely covers a first main face and each side face of the metal plate, and wherein the electrically insulating layer partially covers and partially exposes a second main face of the metal plate, the second main face being opposite from the first main face. 15. The heat spreader of claim 14 , wherein the electrically insulating layer comprises one or more of an imide, a mold material, and a laminate.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • Dispositions of multiple bond pads · CPC title

  • Multiple bond pads having different sizes · CPC title

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Frequently asked questions

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What does patent US9812373B2 cover?
An electronic module includes a semiconductor package including a semiconductor chip and an electrically insulating encapsulation body encapsulating the semiconductor chip, the encapsulation body completely covering a second main face and four side faces of the semiconductor chip, wherein a first main face of the semiconductor chip that is opposite the first main face is exposed from the encaps…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W40/258. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).