Process window optimizer

Patent metadata

Field	Value
Publication number	US-11238189-B2
Application number	US-201815996899-A
Country	US
Kind code	B2
Filing date	Jun 4, 2018
Priority date	Feb 12, 2014
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A defect prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising: identifying a processing window limiting pattern (PWLP) from the pattern; determining a processing parameter under which the PWLP is processed; and determining or predicting, using the processing parameter, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the PWLP with the device manufacturing process.

First claim

The invention claimed is:

1. A defect determination or prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising:
obtaining a spatial distribution of substrate height measurements across the substrate under which a processing window limiting pattern of the pattern is processed, the substrate height measurements obtained before, or during, a processing of the pattern onto or into the substrate; and
determining or predicting, by a hardware computer using a computer model that takes an input to determine a value or computer simulation of at least part of the device manufacturing process and the spatial distribution of substrate height measurements, or one or more values derived therefrom, an existence, a probability of existence, a characteristic, or a combination thereof, of a defect produced from the processing window limiting pattern with the device manufacturing process.

2. The method of claim 1 , wherein the determining or predicting the existence, the probability of existence, the characteristic, or the combination thereof, further uses a characteristic of the processing window limiting pattern, a characteristic of the pattern, or both.

3. The method of claim 1 , further comprising adjusting, using the existence, the probability of existence, the characteristic, or the combination thereof, of the defect, a processing parameter of the device manufacturing process.

4. The method of claim 3 , further comprising determining or predicting, using the adjusted processing parameter, an existence, a probability of existence, a characteristic, or a combination thereof, of a residue defect produced from the processing window limiting pattern using the device manufacturing process.

5. The method of claim 4 , further comprising indicating which one or more of a plurality of processing window limiting patterns to inspect at least partially based on the determined or predicted existence, probability of existence, characteristic, or combination thereof, of the residue defect.

6. The method of claim 1 , further comprising determining a process window of the processing window limiting pattern.

7. The method of claim 6 , wherein the determining or predicting the existence, the probability of existence, the characteristic, or the combination thereof, of the defect comprises comparing the spatial distribution of substrate height measurements, or the one or more values derived therefrom, with the process window.

8. The method of claim 1 , wherein the processing window limiting pattern is identified using an empirical model or a computational model.

9. The method of claim 1 , wherein the determining or predicting the existence, the probability of existence, the characteristic, or the combination thereof, of the defect comprises simulating an image or expected patterning contour of the processing window limiting pattern under the spatial distribution of substrate height measurements, or one or more values derived therefrom and determining an image or contour parameter.

10. A method of manufacturing a device, the method comprising:
performing the method according to claim 1 ; and
indicating which of a plurality of processing window limiting patterns to inspect at least partially based on the determined or predicted existence, probability of existence, characteristic, or the combination thereof, of the defect.

11. A computer program product comprising a non-transitory computer readable medium having instructions therein, the instructions, upon execution by a computer system, configured to cause the computer system to at least:
obtain a spatial distribution of substrate height measurements across a substrate under which a processing window limiting pattern of a pattern is processed, wherein a device manufacturing process is used to process the pattern onto the substrate; and
determine or predict, using a computer model that takes an input to determine a value or computer simulation of at least part of the device manufacturing process and the spatial distribution of substrate height measurements, or one or more values derived therefrom, an existence, a probability of existence, a characteristic, or a combination thereof, of a defect produced from the processing window limiting pattern with the device manufacturing process.

12. The computer program product of claim 11 , further comprising instructions configured to cause the computer system to provide information to enable adjustment, in the device manufacturing process, of a processing parameter using the existence, the probability of existence, the characteristic, or the combination thereof, of the defect.

13. The computer program product of claim 11 , further comprising instructions configured to cause the computer system to determine or predict, using a value of an adjusted processing parameter in the device manufacturing process, an existence, probability of existence, a characteristic, or a combination thereof, of a residue defect produced from the processing window limiting pattern using the device manufacturing process.

14. The computer program product of claim 11 , further comprising instructions configured to cause the computer system to determine a process window of the processing window limiting pattern and further comprising instructions configured to cause the computer system to compare the spatial distribution of substrate height measurements, or the one or more values derived therefrom, with the process window to determine or predict the existence, the probability of existence, the characteristic, or the combination thereof, of the defect.

15. A defect determination or prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising:
obtaining a spatial distribution of substrate height measurements across the substrate under which a processing window limiting pattern of the pattern is processed; and
determining or predicting, by a hardware computer using a computer model that takes an input to determine a value or computer simulation that represents physical manufacture of the pattern into or onto the substrate and the spatial distribution of substrate height measurements, or one or more values derived therefrom, an existence, a probability of existence, a characteristic, or a combination thereof, of a defect produced from the processing window limiting pattern with the device manufacturing process.

16. The method of claim 15 , further comprising adjusting, using the existence, the probability of existence, the characteristic, or the combination thereof, of the defect, a processing parameter of the device manufacturing process.

17. A computer program product comprising a non-transitory computer readable medium having instructions therein, the instructions, upon execution by a computer system, configured to cause the computer system to at least:
obtain a spatial distribution of substrate height measurements across a substrate under which a processing window limiting pattern of a pattern is processed, wherein a device manufacturing process is used to process the pattern onto the substrate; and
determine or predict, using a computer model that takes an input to determine a value or computer simulation that represents physical manufacture of the pattern into or onto the substrate and the spatial distribution of substrate height measurements, or one or more values derived therefrom, an existence, a probability of existence, a characteristic, or a combination thereof, of a defect produced from the processing window limiting patt

Assignees

• Asml Netherlands Bv

Inventors

• Hunsche Stefan
• Vellanki Venugopal

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G03F7/705 Primary

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title

• G03F7/706837

  Data analysis, e.g. filtering, weighting, flyer removal, fingerprints or root cause analysis · CPC title

• G03F7/70525

  Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure · CPC title