Methods, systems, and articles of manufacture for implementing pattern-based design enabled manufacturing of electronic circuit designs

Patent metadata

Field	Value
Publication number	US-9053259-B1
Application number	US-201313802738-A
Country	US
Kind code	B1
Filing date	Mar 14, 2013
Priority date	Nov 28, 2011
Publication date	Jun 9, 2015
Grant date	Jun 9, 2015

Abstract

Some embodiments correlate various manufacturing or design information or data with patterns used to represent electronic designs and provide pertinent pattern-based information to metrology, fabrication, or testing tools to enhance their performances of their intended functions. Some embodiments further utilize cross-design or cross-process analytics to perform various pattern-based analysis on electronic designs. Some embodiments perform squish analysis with a squish pattern library on an electronic design to represent the electronic design with squish patterns by performing pattern matching, pattern decomposition, and pattern classification process.

First claim

We claim:

1. A computer implemented method for performing pattern classification on an electronic design, comprising:
at least one processor or at least one processor core executing a process, the process comprising:
profiling at least a portion of an electronic design against a pattern library including a plurality of patterns to determine a remaining region in the at least a portion of the electronic design; and
identifying a new pattern for storage in the pattern library by at least performing the pattern classification on the remaining region, wherein the new pattern comprises a data structure having multiple binary values.

2. The computer implemented method of claim 1 , the act of performing the pattern classification on the remaining region comprising:
decomposing the remaining region into multiple contexts;
performing the pattern classification on the multiple contexts; and
determining a new pattern based at least in part upon results of performing the pattern classification on the multiple contexts.

3. The computer implemented method of claim 2 , the act of determining the new pattern further comprising:
sampling the remaining region or the multiple contexts to identify multiple patterns having certain topological commonality; and
decomposing each of the multiple patterns into one or more smaller patterns.

4. The computer implemented method of claim 3 , the act of determining the new pattern further comprising:
identifying a sub-pattern that represents the certain topological commonality based at least in part upon results of decomposing the each of the multiple contexts; and
identifying the sub-pattern as the new pattern.

5. The computer implemented method of claim 1 , in which a first pattern in the plurality of patterns comprises a data structure that includes data representing a combination of a topological representation and a logical representation of a geometric pattern in the electronic design.

6. The computer implemented method of claim 2 , in which the act of profiling the at least a portion of an electronic design comprises:
sampling the at least a portion of the electronic design against the plurality of patterns in the pattern library;
identifying one or more matching patterns in the at least a portion of the electronic design that match some of the plurality of patterns in the pattern library;
determining an area covered by the one or more matching patterns in the at least a portion of the electronic design; and
determining the remaining region by excluding the area from the at least a portion of the electronic design.

7. The computer implemented method of claim 1 , the process further comprising:
determining a set of minimal number of unique patterns that jointly represent the at least a portion of the electronic design.

8. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for performing pattern classification on an electronic design, the method comprising:
at least one processor or at least one processor core executing a process, the process comprising:
profiling at least a portion of an electronic design against a pattern library including a plurality of patterns to determining a remaining region in the at least a portion of the electronic design; and
identifying a new pattern for storage in the pattern library by at least performing the pattern classification on the remaining region, wherein the new pattern comprises a data structure having multiple binary values.

9. The article of manufacture of claim 8 , the act of performing the pattern classification on the remaining region comprising:
decomposing the remaining region into multiple contexts;
performing the pattern classification on the multiple contexts; and
determining a new pattern based at least in part upon results of performing the pattern classification on the multiple contexts.

10. The computer implemented method of claim 9 , the act of determining the new pattern further comprising:
sampling the remaining region or the multiple contexts to identify multiple patterns having certain topological commonality; and
decomposing each of the multiple patterns into one or more smaller patterns.

11. The article of manufacture of claim 10 , the act of determining the new pattern further comprising:
identifying a sub-pattern that represents the certain topological commonality based at least in part upon results of decomposing the each of the multiple contexts; and
identifying the sub-pattern as the new pattern.

12. The article of manufacture of claim 8 , in which a first pattern in the plurality of patterns comprises a data structure that includes data representing a combination of a topological representation and a logical representation of a geometric pattern in the electronic design.

13. The article of manufacture of claim 9 , in which the act of profiling the at least a portion of an electronic design comprises:
sampling the at least a portion of the electronic design against the plurality of patterns in the pattern library;
identifying one or more matching patterns in the at least a portion of the electronic design that match some of the plurality of patterns in the pattern library;
determining an area covered by the one or more matching patterns in the at least a portion of the electronic design; and
determining the remaining region by excluding the area from the at least a portion of the electronic design.

14. The article of manufacture of claim 8 , the process further comprising:
determining a set of minimal number of unique patterns that jointly represent the at least a portion of the electronic design.

15. A system for performing pattern classification on an electronic design, comprising:
non-transitory computer accessible storage medium storing thereupon computer code that includes a sequence of instructions;
at least one processor or at least one processor core of a computing system that executes the sequence of instructions to:
profile at least a portion of an electronic design against a pattern library including a plurality of patterns to determining a remaining region in the at least a portion of the electronic design; and
identify a new pattern for storage in the pattern library by at least perform the pattern classification on the remaining region, wherein the new pattern comprises a data structure having multiple binary values.

16. The system of claim 15 , in which the at least one processor or at least one processor core that is to perform the pattern classification on the remaining region is further to:
decompose the remaining region into multiple contexts;
perform the pattern classification on the multiple contexts; and
determine a new pattern based at least in part upon results of performing the pattern classification on the multiple contexts.

17. The system of claim 16 , in which the at least one processor or at least one processor core that is to determine the new pattern is further to:
sample the remaining region or the multiple contexts to identify multiple patterns having certain topological commonality; and
decompose each of the multiple patterns into one or more smaller patterns.

18. The system of claim 17 , in which the at least one processor or at least one processor core that is to determine the new pattern

Assignees

• Cadence Design Systems Inc

Inventors

• Gennari Frank E
• Moskewicz Matthew
• Lai Ya-Chieh

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/50 Primary

  Physics · mapped topic