Virtualization of a reconfigurable data processor

Patent metadata

Field	Value
Publication number	US-11237996-B2
Application number	US-202016862445-A
Country	US
Kind code	B2
Filing date	Apr 29, 2020
Priority date	Jan 3, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.

First claim

What is claimed is:

1. A method for operating one or more reconfigurable processors in a system, comprising
configuring a plurality of virtual machines in respective sets of configurable units in the one or more reconfigurable processors in the system, and starting execution in the plurality of virtual machines; and
stopping and unloading a selected virtual machine in the plurality of virtual machines, and configuring a different virtual machine in the one or more reconfigurable processors using configurable units from the set of configurable units of the selected virtual machine, while other virtual machines in the plurality of virtual machines continue executing.

2. The method of claim 1 , in which the one or more reconfigurable processors comprises an array of configurable units and a bus system connected to the array of configurable units; and wherein configuring a plurality of virtual machines includes
loading configuration data to partition the array of configurable units into the respective sets of configurable units, by blocking communications via the bus system between configurable units inside a particular virtual machine and configurable units outside the particular virtual machine.

3. The method of claim 2 , wherein the configuration data to partition the array includes configuration data for switches on boundaries of the respective sets of configurable units to block communications across the boundaries.

4. The method of claim 1 , in which the one or more reconfigurable processors comprises an array of configurable units and wherein configuring a plurality of virtual machines includes
loading configuration data to confine access to memory outside the array of configurable units originating from within a particular virtual machine in the plurality of virtual machines to memory space allocated to the particular virtual machine.

5. The method of claim 1 , including configuring virtual machines in the plurality of virtual machines to execute application graphs using virtual addresses, and to translate virtual addresses in requests originating from an application graph executing within a particular virtual machine in the plurality of virtual machines, to addresses in the memory space allocated to the particular virtual machine.

6. The method of claim 5 , wherein said configuring virtual machines to translate virtual addresses includes loading a configurable table to map virtual addresses in requests originating from an application graph executing within the particular virtual machine, to addresses in the memory space outside the array of configurable units allocated to the particular virtual machine.

7. The method of claim 1 , wherein the selected virtual machine in the plurality of virtual machines includes a checkpoint, and said stopping and unloading a selected virtual machine stops the virtual machine at the checkpoint.

8. The method of claim 1 , wherein a given reconfigurable data processor of the one or more reconfigurable processors comprises an array of configurable units and a bus system connected to the array of configurable units disposed on a single integrated circuit die or multichip module.

9. The method of claim 8 , wherein the given reconfigurable data processor of the one or more reconfigurable processors, comprises a plurality of tiles, and at least one virtual machine in the plurality of virtual machines includes configurable units in more than one tile in the plurality of tiles.

10. The method of claim 1 , wherein the system comprises a plurality of reconfigurable processors disposed on respective integrated circuits, and the selected virtual machine includes configurable units in more than one of the integrated circuits.

11. A system comprising one or more reconfigurable processors, comprising:
one or more reconfigurable processors;
a processor operatively coupled to the one or more reconfigurable processors, the processor configured to execute a host program, the host program executable:
to configure a plurality of virtual machines in respective sets of configurable units in the one or more reconfigurable processors;
to start execution in the plurality of virtual machines; and
to stop and unload a selected virtual machine in the plurality of virtual machines, and configure a different virtual machine in the one or more reconfigurable processors using configurable units from the set of configurable units of the selected virtual machine, while other virtual machines in the plurality of virtual machines continue executing.

12. The system of claim 11 , in which the one or more reconfigurable processors comprises an array of configurable units and a bus system connected to the array of configurable units; wherein the host program is executable to configure a plurality of virtual machines includes
logic to load configuration data to partition the array of configurable units into the respective sets of configurable units, by blocking communications via the bus system between configurable units inside a particular virtual machine and configurable units outside the particular virtual machine.

13. The system of claim 12 , wherein the configuration data to partition the array includes configuration data for switches on boundaries of the respective sets of configurable units to block communications across the boundaries.

14. The system of claim 11 , wherein the host program is executable to configure a plurality of virtual machines includes
logic to load configuration data to confine access to memory outside the set of configurable units originating from within a particular virtual machine in the plurality of virtual machines to memory space allocated to the particular virtual machine.

15. The system of claim 11 , wherein the host program is executable to configure virtual machines in the plurality of virtual machines to execute application graphs using virtual addresses, and to translate virtual addresses in requests originating from an application graph executing within a particular virtual machine in the plurality of virtual machines, to addresses in the memory space allocated to the particular virtual machine.

16. The system of claim 15 , wherein said logic to configure virtual machines to translate virtual addresses includes loading a configurable table to map virtual addresses in requests originating from an application graph executing within the particular virtual machine, to addresses in the memory space outside the array of configurable units allocated to the particular virtual machine.

17. The system of claim 11 , wherein the selected virtual machine in the plurality of virtual machines includes a checkpoint, and said logic to stop and unload a selected virtual machine stops the virtual machine at the checkpoint.

18. The system of claim 11 , wherein a given reconfigurable data processor of the one or more reconfigurable processors comprises an array of configurable units and a bus system connected to the array of configurable units disposed on a single integrated circuit die or multichip module.

19. The system of claim 18 , wherein the given reconfigurable data processor of the one or more reconfigurable processors, comprises a plurality of tiles, and at least one virtual machine in the plurality of virtual machines includes configurable units in more than one tile in the plurality of tiles.

20. The system of claim 11 , wherein the system comprises a plurality of reconfigurable processors disposed on respective integrated circuits, and the selected virtual machine includes configurable uni

Assignees

• Sambanova Systems Inc

Inventors

• Grohoski Gregory Frederick
• Jairath Sumti
• Luttrell Mark
• Prabhakar Raghu
• Sivaramakrishnan Ram
• Shah Manish K

Classifications

• G06F12/10

  Address translation · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F15/7839

  with memory · CPC title

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title