Three-dimensional memory device containing compositionally graded word line diffusion barrier layer for and methods of forming the same

US11217532B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11217532-B2
Application numberUS-201816020008-A
CountryUS
Kind codeB2
Filing dateJun 27, 2018
Priority dateMar 14, 2018
Publication dateJan 4, 2022
Grant dateJan 4, 2022

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Abstract

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A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

First claim

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What is claimed is: 1. A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting the memory film, wherein: each of the electrically conductive layers comprises a stack of a compositionally graded diffusion barrier and a metal fill material portion; the compositionally graded diffusion barrier comprises a substantially amorphous region contacting the metal fill material portion and a substantially crystalline region that is spaced from an interface between the compositionally graded diffusion barrier and the metal fill material portion by the amorphous region; and the substantially amorphous region and the substantially crystalline region of the compositionally graded diffusion barrier have a composition of Ti α X β N or W α X β N, wherein α increases with a distance from the interface and β decreases with the distance from the interface, wherein α is greater in the substantially crystalline region of the compositionally graded diffusion barrier than in the substantially amorphous region of the compositionally graded diffusion barrier, and wherein β is greater in the substantially amorphous region of the compositionally graded diffusion barrier than in the substantially crystalline region of the compositionally graded diffusion barrier, and X is selected from Si, B, Al, O, and C. 2. The three-dimensional memory device of claim 1 , wherein: the substantially amorphous region is at least 80 volume percent amorphous and has a continuous thickness throughout the compositionally graded diffusion barrier; the substantially crystalline region is at least 80 volume percent crystalline; a partially crystalline region is located between the substantially amorphous region and the substantially crystalline region; the partially crystalline region is greater than 20 and less than 80 volume percent crystalline and greater than 20 and less than 80 volume percent amorphous; and a crystallinity of the compositionally graded diffusion barrier gradually monotonically increases from the substantially amorphous region through the partially crystalline region to the substantially crystalline region. 3. The three-dimensional memory device of claim 1 , further comprising a backside blocking dielectric layer located between each vertically neighboring pair of an electrically conductive layer and an insulating layer and contacting a respective compositionally graded diffusion barrier. 4. The three-dimensional memory device of claim 3 , wherein the compositionally graded diffusion barrier comprises an interfacial region that consists essentially of TiN or WN and located at an interface with the backside blocking dielectric layer and β has a value of 0 within the interfacial region. 5. The three-dimensional memory device of claim 4 , wherein: the substantially crystalline material composition comprises a region including TiN or WN; and the substantially amorphous material composition comprises a region including silicon nitride, boron nitride, or aluminum nitride. 6. The three-dimensional memory device of claim 4 , wherein: the substantially crystalline material composition comprises a region consisting essentially of TiN or WN; and the substantially amorphous material composition comprises a region consisting essentially of silicon nitride, boron nitride, or aluminum nitride. 7. The three-dimensional memory device of claim 4 , wherein: the substantially crystalline material composition comprises a region including TiN; and the substantially amorphous material composition comprises a region including titanium silicon nitride or titanium carbonitride. 8. The three-dimensional memory device of claim 1 , wherein: α changes at least by 0.1 within the compositionally graded diffusion barrier; and β changes at least by 0.1 within the compositionally graded diffusion barrier. 9. The three-dimensional memory device of claim 1 , wherein β has a value of zero at a surface of the compositionally graded diffusion barrier that does not contact the metal fill material portion, and wherein α has a value in a range from 0.75 to 1.67 at the surface of the compositionally graded diffusion barrier that does not contact the metal fill material portion. 10. The three-dimensional memory device of claim 1 , wherein the metal fill material portion comprises a tungsten portion, and the amorphous region of the compositionally graded diffusion barrier comprises a titanium silicon nitride region. 11. The three-dimensional memory device of claim 1 , wherein X is selected from Si, B, Al, and O, and α has a non-zero value at the interface between the compositionally graded diffusion barrier and the metal fill material portion. 12. The three-dimensional memory device of claim 1 , wherein X is selected from Si, B, and Al, and α is zero at the interface between the compositionally graded diffusion barrier and the metal fill material portion. 13. A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting the memory film, wherein: each of the electrically conductive layers comprises a stack of a compositionally graded diffusion barrier and a metal fill material portion; the compositionally graded diffusion barrier comprises a substantially amorphous region contacting the metal fill material portion and a substantially crystalline region that is spaced from an interface between the compositionally graded diffusion barrier and the metal fill material portion by the amorphous region; each of the substantially amorphous region and substantially crystalline region of the compositionally graded diffusion barrier has a respective composition of TiN γ Q δ , wherein γ increases with a distance from an interface between the compositionally graded diffusion barrier and the metal fill material portion and δ decreases with the distance from the interface between the compositionally graded diffusion barrier and the metal fill material portion, wherein γ is greater in the substantially crystalline region of the compositionally graded diffusion barrier than in the substantially amorphous region of the compositionally graded diffusion barrier, and wherein δ is greater in the substantially amorphous region of the compositionally graded diffusion barrier than in the substantially crystalline region of the compositionally graded diffusion barrier, and Q is selected from Si and C. 14. The three-dimensional memory device of claim 13 , wherein δ has a value of zero at a surface of the compositionally graded diffusion barrier that does not contact the metal fill material portion. 15. The three-dimensional memory device of claim 13 , further comprising a backside blocking dielectric layer located between each vertically neighboring pair of an electrically conductive layer and an insulating layer and contacting a respective compositionally graded diffusion barrier, wherein the compositionally graded diffusion barrier comprises a nucleation region that consists essentially of titanium and nitrogen and located at an interface with the backside blocking dielectric layer and δ has a value of 0 within the interfacial region.

Assignees

Inventors

Classifications

  • combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

  • H10W20/425Primary

    Barrier, adhesion or liner layers · CPC title

  • the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US11217532B2 cover?
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion b…
Who is the assignee on this patent?
Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 04 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).