Metal word lines for three dimensional memory devices

Patent metadata

Field	Value
Publication number	US-2016148945-A1
Application number	US-201414553207-A
Country	US
Kind code	A1
Filing date	Nov 25, 2014
Priority date	Nov 25, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions.

First claim

What is claimed is:

1 . A method of making a monolithic three dimensional NAND string, comprising:
forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate; forming a front side opening in the stack; forming at least one charge storage region in the front side opening; forming a tunnel dielectric layer over the at least one charge storage region in front side opening; forming a semiconductor channel over the tunnel dielectric layer in the front side opening; forming a back side opening in the stack; selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers; forming electrically conductive clam shaped nucleation liner regions in the back side recesses; and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions.

2 . The method of claim 1 , further comprising forming a blocking dielectric between the control gate electrodes and the at least one charge storage region.

3 . The method of claim 2 , wherein:
the step of selectively removing at least portions of the first material layers comprises selectively etching the first material layers through the back side opening to form the back side recesses; the step of forming the blocking dielectric comprises forming the blocking dielectric in the front side opening over the at least one charge storage region, or through the back side opening in the back side recesses on exposed portions of the at least one charge storage region; and the step of selectively forming the ruthenium control gate electrodes comprises selectively forming ruthenium regions on respective the electrically conductive clam shaped nucleation liner regions without forming ruthenium on sidewalls of the first material layers exposed in the back side opening in the stack.

4 . The method of claim 3 , wherein forming the electrically conductive clam shaped nucleation liner regions in the back side recesses comprises forming an electrically conductive nucleation layer in the back side opening and in the back side recesses followed by removing the nucleation liner from the back side opening to expose sidewalls of the first material layers in the back side opening.

5 . The method of claim 4 , wherein selectively forming the ruthenium control gate electrodes comprises selectively forming the ruthenium control gate electrodes by atomic layer deposition.

6 . The method of claim 5 , wherein:
the electrically conductive clam shaped nucleation liner regions comprise at least one of tungsten, tungsten nitride, titanium nitride, ruthenium nitride or tantalum nitride; and the first material layers comprise silicon oxide layers.

7 . The method of claim 6 , wherein horizontal portions of the electrically conductive clam shaped nucleation liner regions have a smaller thickness in a direction perpendicular to the major surface of the substrate than the ruthenium control gate electrodes.

8 . The method of claim 6 , wherein:
the electrically conductive clam shaped nucleation liner regions have a thickness of 2 to 5 nm; the ruthenium control gate electrodes have a thickness of 10 to 25 nm in a direction perpendicular to the major surface of the substrate; and the back side recesses have thickness of 15 to 30 nm in the direction perpendicular to the major surface of the substrate.

9 . The method of claim 6 , wherein a thickness of the ruthenium control gate electrodes in the direction perpendicular to the major surface of the substrate is less than twice a thickness at which onset of growth of ruthenium begins on the first material layers exposed in the back side opening or on the blocking dielectric if the blocking dielectric is exposed in the back side opening.

10 . The method of claim 6 , wherein:
the ruthenium control gate electrodes are selectively formed by atomic layer deposition for a first number of atomic layer deposition cycles; the first number of atomic layer deposition cycles is greater than or equal to a number of cycles required to completely fill recesses in the electrically conductive clam shaped nucleation liner regions with ruthenium; and the first number of cycles is less than a number of cycles at which ruthenium incubation delay on the first material layers ends, and at which ruthenium deposits on the first material layers.

11 . The method of claim 5 , wherein selectively forming the ruthenium control gate electrodes by atomic layer deposition comprises:
(a) using a RuO 4 precursor to deposit one or more RuO 2 monolayers using atomic layer deposition; (b) exposing the one or more RuO 2 monolayers to a reducing atmosphere to reduce the deposited one or more RuO 2 monolayers to one or more Ru monolayers; and (c) repeating steps (a) and (b) a plurality of times to selectively form the ruthenium control gate electrodes.

12 . The method of claim 2 , wherein:
the at least one charge storage region comprises a plurality of floating gates or a charge storage dielectric layer formed in the front side opening; the semiconductor channel comprises polysilicon or amorphous silicon; the blocking dielectric comprises a metal oxide blocking dielectric; the first material layers comprise silicon oxide layers; and the second material layers comprise silicon nitride or polysilicon layers.

13 . The method of claim 1 , further comprising:
forming a source region of the NAND string in or over the substrate through the back side opening; forming an insulating layer in the back side opening; removing a bottom portion of the insulating layer to expose the source region; and forming a source line in the back side opening in contact with the source region.

14 . The method of claim 13 , wherein:
the substrate comprises a silicon substrate; the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate; the control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.

15 . A monolithic three dimensional NAND string, comprising:
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate; a plurality of ruthenium control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level; electrically conductive clam shaped nucleation liner regions located in contact with the plurality of ruthenium control gate electrodes; a blocking dielectric located in contact with the electrically conductive clam shaped nucleation liner regions; at least one charge storage region located in

Assignees

• Sandisk Technologies Inc

Inventors

• Sharangpani Rahul
• Makala Raghuveer S
• Kanakamedala Senaka Krishna
• Koka Sateesh
• Lee Yao-Sheng
• Matamis George

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title