Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11177282-B2
Application number	US-202016921185-A
Country	US
Kind code	B2
Filing date	Jul 6, 2020
Priority date	Jul 25, 2017
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a cell array region and a connection region;
a stack structure comprising a plurality of conductive layers stacked on the substrate, a first one of the plurality of conductive layers comprising a pad region that protrudes relative to an overlying second one of the plurality of conductive layers on the connection region;
a vertical structure on the cell array region and penetrating the stack structure;
a support structure penetrating the pad region; and
a contact plug connected with a center of the pad region,
wherein a first portion of the support structure extends in a first direction, intersecting a second direction that is toward the contact plug, in a first plane parallel to an upper surface of the substrate,
wherein a second portion of the support structure extends in the first direction in a second plane that is at a lower level than the first plane, and
wherein a first shape of the first portion of the support structure in the first plane is different from a second shape of the second portion of the support structure in the second plane.

2. The semiconductor device of claim 1 , wherein, in a horizontal cross-sectional view, the first shape of the first portion of the support structure in the first plane and the second shape of the second portion of the support structure in the second plane comprise an elliptical shape comprising a major axis that extends in the first direction or a bar shape extending in the first direction.

3. The semiconductor device of claim 1 , wherein a horizontal section of the first portion of the support structure in the first plane has a size larger than that of a horizontal section of the second portion of the support structure in the second plane.

4. The semiconductor device of claim 1 ,
wherein the support structure is one among a plurality of support structures, and
wherein the plurality of support structures comprise four support structures that are each adjacent to an edge of the pad region.

5. The semiconductor device of claim 4 , wherein, in a horizontal cross-sectional view, the contact plug is located between the four support structures.

6. The semiconductor device of claim 4 , wherein, in a horizontal cross-sectional view, the four support structures are symmetrical with each other about the contact plug.

7. The semiconductor device of claim 1 , wherein the support structure comprises:
a dummy lower semiconductor pattern on the substrate; and
a dummy conductive pad on the dummy lower semiconductor pattern.

8. The semiconductor device of claim 7 , wherein the support structure further comprises a dummy upper semiconductor pattern between the dummy lower semiconductor pattern and the dummy conductive pad.

9. The semiconductor device of claim 1 , wherein the vertical structure comprises:
a lower semiconductor pattern on the substrate;
a conductive pad on the lower semiconductor pattern; and
an upper semiconductor pattern between the lower semiconductor pattern and the conductive pad.

10. The semiconductor device of claim 1 , wherein a lowermost surface of the support structure is in contact with the substrate.

11. The semiconductor device of claim 1 ,
wherein the stack structure comprising a stepped structure on the connection region, and
wherein the support structure penetrates the stepped structure on the connection region.

12. A semiconductor device comprising:
a substrate;
a stack structure comprising conductive layers stacked on the substrate, a first one of the conductive layers comprising a pad region that protrudes relative to an overlying second one of the conductive layers in a stepped region of the stack structure; and
a support structure penetrating the pad region on the stepped region of the stack structure,
wherein the support structure comprises:
an elliptical shape, in a horizontal cross-sectional view, comprising a minor axis that extends in a first direction toward a center of the pad region; or
a bar shape, in the horizontal cross-sectional view, extending in the first direction, and
wherein a horizontal section of a first portion of the support structure in a first plane parallel to an upper surface of the substrate has a size larger than that of a horizontal section of a second portion of the support structure in a second plane that is at a lower level than the first plane.

13. The semiconductor device of claim 12 , further comprising a contact plug comprising a conductive material that is on the center of the pad region.

14. The semiconductor device of claim 13 ,
wherein the support structure is one among a plurality of support structures, and
wherein the plurality of support structures comprise four support structures that are each adjacent to an edge of the pad region.

15. The semiconductor device of claim 14 , wherein, in the horizontal cross-sectional view, the contact plug is located between the four support structures.

16. The semiconductor device of claim 14 , wherein, in the horizontal cross-sectional view, the four support structures are symmetrical with each other about the contact plug.

17. The semiconductor device of claim 12 , wherein the support structure comprises:
a dummy lower semiconductor pattern on the substrate; and
a dummy conductive pad on the dummy lower semiconductor pattern.

18. The semiconductor device of claim 17 , wherein the support structure further comprises a dummy upper semiconductor pattern between the dummy lower semiconductor pattern and the dummy conductive pad.

19. The semiconductor device of claim 12 , further comprising a vertical structure on the substrate and penetrating the stack structure,
wherein the vertical structure comprises:
a lower semiconductor pattern on the substrate;
a conductive pad on the lower semiconductor pattern; and
an upper semiconductor pattern between the lower semiconductor pattern and the conductive pad.

20. The semiconductor device of claim 12 , wherein a lowermost surface of the support structure is in contact with the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Kwangyoung
• Kim Jongwon
• Eun Dongseog
• Lee Joonhee

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title