Passive devices for integration with three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-9646981-B2
Application number	US-201514739284-A
Country	US
Kind code	B2
Filing date	Jun 15, 2015
Priority date	Jun 15, 2015
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.

First claim

What is claimed is:

1. A three dimensional memory device, comprising:
a memory device region containing a plurality of non-volatile memory devices;
a peripheral device region containing active driver circuit devices;
a first stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices;
a stack of alternating layers including electrically insulating layers and electrically conductive layers located over a substrate, wherein the first stepped surface region contains first portions of the electrically insulating layers and first portions of the electrically conductive layers, and the first stepped region is located on a first side of the stack;
a second stepped surface region containing second portions of the electrically insulating layers and second portions of the electrically conductive layers located on a second side of the stack;
a plurality of semiconductor channels located in the memory device region in the stack, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels;
a plurality of passive device contact via structures extending substantially perpendicular to the top surface of the substrate to the respective first portions of the electrically conductive layers in the first stepped surface region; and
a plurality of control gate contact via structures extending substantially perpendicular to the top surface of the substrate to the respective second portions of the electrically conductive layers in the second stepped surface region,
wherein:
the peripheral device region contains sense amplifiers;
the second stepped surface region comprises a word line stepped surface region for the plurality of non-volatile memory devices;
the second portions of the electrically conductive layers comprise a plurality of control gate electrodes extending substantially parallel to the top surface of the substrate, and the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the memory device region and the plurality of passive driver circuit devices are laterally separated from, and electrically isolated from, each other by a support pillar trench that vertically extends through an entirety of the stack of alternating layers and laterally extends along a same lateral direction as stepped surfaces within the first stepped surface region and a dielectric pillar structure located within the support pillar trench including a first dielectric fill material.

2. The device of claim 1 , wherein:
the plurality of passive driver circuit devices comprise a plurality of capacitors;
the first portions of the electrically conductive layers comprise a plurality of capacitor electrodes;
the first portions of the electrically insulating layers comprise capacitor dielectrics located between the capacitor electrodes; and
the respective first and the second portions of each of the electrically conductive layer are located at the same level above the substrate and are electrically insulated from each other.

3. The device of claim 1 , wherein the plurality of passive driver circuit devices comprises a plurality of resistors.

4. A method of forming a memory device comprising:
forming a plurality of memory devices in a memory device region;
forming a plurality of passive devices outside the memory device region;
forming a conductive layer in one deposition step such that a first portion of the conductive layer comprises a portion of at least one of the passive device and a second portion of the conductive layer forms a portion of at least one memory device;
forming a stack comprising an alternating plurality of electrically insulating layers and second material layers over a substrate;
forming trenches extending through the stack of alternating layers, wherein sidewalls of a patterned portion of the stack of alternating layers are physically exposed, and wherein forming trenches comprises forming a support pillar trench vertically extending through the stack of alternating layers and laterally extending along a same lateral direction as stepped surfaces of the first stepped surface region;
forming a dielectric pillar structure in the support pillar trench by depositing a first dielectric fill material,
forming a patterned stack comprising an alternating plurality of the electrically insulating layers and electrically conductive layers, wherein the electrically conductive layers in the patterned stack are formed at each level of the second material layers, and the patterned stack is laterally contacted by a set of dielectric fill material portions formed within trenches;

wherein:
portions of the electrically conductive layers located in a first stepped surface region between a peripheral device region and a memory device region constitute at least a portion of passive devices;
additional portions of the electrically conductive layers located in a second stepped surface region comprises a word line stepped surface region for the plurality of memory devices;
forming the conductive layer comprises forming at least one of the electrically conductive layers or at least one of the plurality of contact via structures;
the passive devices comprise capacitors;
a subset of the electrically insulating layers located in the first stepped surface region constitutes node dielectrics of the set of capacitors; and
each capacitor in the set comprises:
a first node that includes an underlying electrically conductive layer of a respective vertically neighboring pair and a respective contact via structure that extends upward from the underlying electrically conductive layer and through the dielectric material portion; and
a second node that includes an overlying electrically conductive layer of the respective vertically neighboring pair and a respective contact via structure that extends upward from the overlying electrically conductive layer and through the dielectric material portion,

and wherein the memory device region and the portion of passive devices are laterally separated from, and electrically isolated from, each other by the support pillar trench and the dielectric pillar structure.

5. The method of claim 4 , further comprising replacing the second material layers with conductive material portions;
wherein:
the electrically conductive layers in the patterned stack comprises remaining portions of the conductive material portions;
the set of dielectric fill material portions is formed within the trenches after replacement of the second material layers with the conductive material portions; and
the second material layers are replaced with the conductive material portions by:
forming lateral recesses by etching the second material layers by introducing an etchant through one or more of the trenches;
depositing the conductive material portions within the lateral recesses; and
filling the one or more of the trenches with one or more dielectric fill material portions within the set of dielectric fill material portions.

6. The method of claim 4 , further comprising:
filling each of the trenches with a dielectric material of a respective dielectric fill material portion;
forming a stepped surface region in which each underlying second material layer laterally extends farther than any overlying second material layer thereof; and
forming a dielectric material portion over the stepped surface region.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Nishikawa Masatoshi
• Honma Ryoichi
• Miwa Toru
• Matsumoto Masahide
• Mizutani Yuki
• Koketsu Hiroaki

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L27/11526 Primary

  Electricity · mapped topic

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• H01L27/11573

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic