Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9559049-B1
Application number	US-201514827971-A
Country	US
Kind code	B1
Filing date	Aug 17, 2015
Priority date	Aug 17, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of first conductive line layers extending along a plane defined by a first direction and a second direction, wherein each of the first conductive line layers comprises a plurality of first conductive lines extending in the first direction;
a plurality of support structures disposed between the adjacent first conductive line layers, wherein the support structures and the first conductive lines have different shapes; and
a charge storage layer touching upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

2. The memory device according to claim 1 , wherein the first conductive lines and the support structures are formed of different materials.

3. The memory device according to claim 1 , wherein the material of the support structures comprises an insulating material, a dielectric material, a low-k material, or a combination thereof.

4. The memory device according to claim 3 , wherein the material of the support structure comprises SiO, SiN, SiON, SiOC, SiC, SiOF, SiOH, or a combination thereof.

5. The memory device according to claim 1 , wherein each of the support structures is a continuous support structure and further passes through the first conductive lines.

6. The memory device according to claim 1 , wherein the support structures comprise a pillar structure, a wave structure, a sheet structure, a corrugated structure, or a combination thereof.

7. The memory device according to claim 1 , wherein the support structures comprise a plurality of pillar structures, and a profile of two sidewalls of the pillar structures comprises a rectangle, a trapezoid, a hourglass shape, an egg shape, an irregular shape, or a combination thereof.

8. The memory device according to claim 1 , wherein a shape of an upper surface of the support structures comprises a circle, an ellipse, a square, a star shape, a heart shape, a mushroom shape, a double-peak shape, a bowknot shape, or a combination thereof.

9. The memory device according to claim 1 , further comprising a plurality of second conductive line layers, wherein each of the second conductive line layers extends along a plane defined by the second direction and a third direction, and each of the second conductive line layers is disposed between adjacent two support structures and surrounds a portion of the charge storage layer around the corresponding one of the first conductive lines, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

10. The memory device according to claim 9 , comprising a plurality of memory cells that are arranged in a three-dimensional array, wherein each of the memory cells comprises a portion of one of the first conductive lines, a portion of the charge storage layer surrounding the corresponding one of the first conductive lines, and a portion of one of the second conductive line layers covering the corresponding charge storage layer.

11. The memory device according to claim 10 , wherein at least one support structure is disposed between adjacent two memory cells.

12. The memory device according to claim 9 , further comprising a plurality of dielectric pillars extending in the third direction and arranged alternately with the second conductive line layers in the first direction.

13. A memory device, comprising:
a plurality of first conductive line layers extending along a plane defined by a first direction and a second direction, wherein each of the first conductive line layers comprises a plurality of first conductive lines extending in the first direction, and each of the first conductive lines includes a plurality of wide portions and a plurality of narrow portions that are arranged alternately;
a plurality of support structures disposed between the adjacent first conductive line layers, wherein the support structures and the first conductive lines have different shapes; and
a charge storage layer covering upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

14. The memory device according to claim 13 , wherein the first conductive lines and the support structures are formed of different materials.

15. The memory device according to claim 13 , wherein the material of the support structures comprises an insulating material, a dielectric material, a low-k material, or a combination thereof.

16. The memory device according to claim 13 , wherein each of the support structures is a continuous support structure and further passes through the first conductive lines.

17. The memory device according to claim 13 , further comprising a plurality of second conductive line layers, wherein each of the second conductive line layers extends along a plane defined by the second direction and a third direction, and each of the second conductive line layers is disposed between adjacent two support structures and surrounds a portion of the charge storage layer around the corresponding one of the first conductive lines, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

18. The memory device according to claim 17 , comprising a plurality of memory cells that are arranged in a three-dimensional array, wherein each of the memory cells comprises a portion of one of the first conductive lines, a portion of the charge storage layer surrounding the corresponding one of the first conductive lines, and a portion of one of the second conductive line layers covering the corresponding charge storage layer.

19. The memory device according to claim 18 , wherein at least one support structure is disposed between adjacent two memory cells.

20. The memory device according to claim 17 , further comprising a plurality of dielectric pillars extending in the third direction and arranged alternately with the second conductive line layers in the first direction.

Assignees

• Macronix Int Co Ltd

Inventors

• Chiu Yuan-Chieh
• Hong Shih-Ping
• Chung Yao-An

Classifications

• H10W70/095

  of vias therein · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title