Prefetch insensitive transactional memory

Patent metadata

Field	Value
Publication number	US-10042749-B2
Application number	US-201514937036-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Nov 10, 2015
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. A processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction by providing a requested prefetch data by providing a requested prefetch data. A processor responds to a determination that the prefetch request conflicts with a transaction by suppressing a processing of the prefetch request.

First claim

What is claimed is:

1. A computer program product for controlling abort operations during processing of prefetch memory operations and transactions, the program instructions comprising:
one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising:
program instructions to receive by a local processor a prefetch request from a remote processor;
program instructions to, prior to execution of the prefetch request, determine whether execution of the prefetch request is predicted to cause a conflict during an execution of a transaction of the local processor based on one or more of (i) a comparison of a priority of the prefetch request with a priority of the transaction, and (ii) a comparison of a priority of the local processor with a priority of the remote processor; and
program instructions to respond to at least one of (i) a determination that the priority of the prefetch request is greater than priority of the transaction, and (ii) a determination that the priority of the remote processor is greater than priority of the local processor by executing the prefetch request and providing requested prefetch data to the remote processor.

2. The computer program product of claim 1 , wherein the prefetch request is at least one of (i) a read prefetch request, and (ii) a write prefetch request that includes program instructions to move data from a first memory to a second memory based on an anticipated access of the data by the remote processor, wherein the second memory has a lower memory level relative to the remote processor when compared with a memory level of the first memory relative to the remote processor.

3. The computer program product of claim 1 , further comprising:
program instructions to respond to a determination that an execution of a given prefetch request is predicted to cause a conflict during the execution of a given transaction by suppressing the execution of the given prefetch request by executing an abort of the given prefetch request, wherein at least one of (i) the priority of the prefetch request is lower than priority of the transaction, and (ii) the priority of the remote processor is lower than priority of the local processor.

4. The computer program product of claim 3 , further comprising:
program instructions to send a notification to the remote processor that indicates that the given prefetch request was aborted.

5. The computer program product of claim 3 , further comprising:
program instruction to respond to a determination that an execution of the given prefetch request is predicted to cause a conflict during the execution of the given transaction by suppressing the execution of the given prefetch request by queuing the given prefetch request in a queue.

6. The computer program product of claim 5 , further comprising:
program instructions to notify the remote processor that the given prefetch request is queued in the queue.

7. The computer program product of claim 5 , further comprising:
program instructions to remove the given prefetch request from the queue; and
program instructions to execute the given prefetch request if the memory address associated with the given prefetch request after the given transaction is processed.

8. The computer program product of claim 7 , further comprising:
program instructions to notify the remote processor that the given prefetch request was executed.

9. The computer program product of claim 3 , further comprising:
program instructions to respond to a determination that an execution of the given prefetch request is predicted to cause a conflict during the execution of the given transaction by suppressing, at least in part, the execution of the given prefetch request by executing a delay before the execution of the given prefetch request is performed, wherein a duration of the delay is determined by one or both of (i) one or more conditions in the local processor, and (ii) one or more conditions in the remote processor.

10. A computer system for controlling abort operations during processing of prefetch memory operations and transactions, the computer system comprising:
one or more computer processors, one or more computer readable storage media, and program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising:
program instructions to receive by a local processor a prefetch request from a remote processor;
program instructions to, prior to execution of the prefetch request, determine whether execution of the prefetch request is predicted to cause a conflict during an execution of a transaction of the local processor based on one or more of (i) a comparison of a priority of the prefetch request with a priority of the transaction, and (ii) a comparison of a priority of the local processor with a priority of the remote processor; and
program instructions to respond to at least one of (i) a determination that the priority of the prefetch request is greater than priority of the transaction, and (ii) a determination that the priority of the remote processor is greater than priority of the local processor by executing the prefetch request and providing requested prefetch data to the remote processor.

11. The computer system of claim 10 , wherein the prefetch request is at least one of (i) a read prefetch request, and (ii) a write prefetch request that includes program instructions to move data from a first memory to a second memory based on an anticipated access of the data by the remote processor, wherein the second memory has a lower memory level relative to the remote processor when compared with a memory level of the first memory relative to the remote processor.

12. The computer system of claim 10 , further comprising:
program instructions to respond to a determination that an execution of a given prefetch request is predicted to cause a conflict during the execution of a given transaction by suppressing the execution of the given prefetch request by executing an abort of the given prefetch request, wherein at least one of (i) the priority of the prefetch request is lower than priority of the transaction, and (ii) the priority of the remote processor is lower than priority of the local processor.

13. The computer system of claim 12 , further comprising:
program instructions to send a notification to the remote processor that indicates that the given prefetch request was aborted.

14. The computer system of claim 12 , further comprising:
program instruction to respond to a determination that an execution of the given prefetch request is predicted to cause a conflict during the execution of the given transaction by suppressing the execution of the given prefetch request by queuing the given prefetch request in a queue.

15. The computer system of claim 14 , further comprising:
program instructions to notify the remote processor that the given prefetch request is queued in the queue.

16. The computer system of claim 14 , further comprising:
program instructions to remove the given prefetch request from the queue; and
program instructions to execute the given prefetch request if the memory address associated with the given prefetch request after the given transaction is processed.

17. The computer system of claim 16 , further comprising:
program instructions to notify the remote processor that the given prefetch request was executed.

18. The computer s

Assignees

• IBM

Inventors

• Gschwind Michael Karl
• Salapura Valentina
• Shum Chung-Lung K
• Slegel Timothy J

Classifications

• G06F2212/281

  Single cache · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F2212/70

  Details relating to dynamic memory management · CPC title

• G06F12/0215 Primary

  with look ahead addressing means · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title