LPS solder paste based low cost fine pitch pop interconnect solutions

US9831206B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9831206-B2
Application numberUS-201414229785-A
CountryUS
Kind codeB2
Filing dateMar 28, 2014
Priority dateMar 28, 2014
Publication dateNov 28, 2017
Grant dateNov 28, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor package comprising: a first substrate having a plurality of first contact pads formed on an interior region of the first substrate and a plurality of second contact pads formed on a peripheral region of the first substrate; a first device die comprising a plurality of first bonding pads, each electrically coupled to one of the first contact pads by a solder bump; and a second substrate positioned above the first device die, and having a plurality of second bonding pads, each electrically coupled to one of the second contact pads by an interconnect comprising a no-slump solder paste and having an aspect ratio of 2:1 or greater, and wherein the no-slump solder paste comprises a conductive network formed by particles of a high-melting point metal, a solder matrix including an alloy of two or more elements, and a delivery vehicle, wherein the particles of the high-melting point metal are separated from the delivery vehicle by intermetallic compound shells that surround the high-melting point metal and are formed from the solder-matrix material and the high-melting point metal, and wherein the solder matrix forms conductive bridges between the high-melting point metal particles, and wherein each interconnect comprises unsupported sidewalls. 2. The semiconductor package of claim 1 , wherein the particles of the high-melting point metal are copper particles, the solder matrix is a SnBi solder, and the delivery vehicle comprises a polymer matrix. 3. The semiconductor package of claim 1 , wherein the interconnects have a height greater than 400 μm. 4. The semiconductor package of claim 1 , wherein the interconnects have a pitch less than 0.35 mm. 5. The semiconductor package of claim 1 , wherein the interconnects comprise a first portion and a second portion, wherein the first portion is bonded and electrically coupled to the second portion. 6. The semiconductor package of claim 5 , wherein the first portion and the second portion are a no-slump solder paste comprising copper particles, a solder material, and a delivery vehicle. 7. The semiconductor package of claim 5 , wherein the first portion is a solder bump and the second portion is a no-slump solder paste comprising copper particles, a solder material, and a delivery vehicle. 8. The semiconductor package of claim 5 , wherein the first portion is a no-slump solder paste comprising copper particles, a solder material, and a polymer matrix, and the second portion is a solder bump.

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What does patent US9831206B2 cover?
Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).