Methods of selective removal of blocking dielectric in NAND memory strings

Patent metadata

Field	Value
Publication number	US-9230974-B1
Application number	US-201414468743-A
Country	US
Kind code	B1
Filing date	Aug 26, 2014
Priority date	Aug 26, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Methods of making a monolithic three dimensional NAND string may enable selective removal of a blocking dielectric material, such as aluminum oxide, without otherwise damaging the device. Blocking dielectric may be selectively removed from the back side (e.g., slit trench) and/or front side (e.g., memory opening) of the NAND string. Also disclosed are NAND strings made in accordance with the embodiment methods.

First claim

What is claimed is:

1. A method of making a monolithic, three dimensional NAND string, comprising:
forming a stack of alternating layers of a first material and a second material different than the first material over a substrate;
etching the stack to form a front side opening in the stack;
forming at least one memory film over a sidewall of the front side opening;
forming a semiconductor channel over the at least one memory film in the front side opening;
etching the stack to form a back side opening in the stack, the backside opening including a pair of oppositely disposed sidewalls and a bottom surface;
removing by etching at least a portion of the second material layers through the back side opening to form back side recesses between the first material layers;
forming a blocking dielectric over the sidewalls and bottom surface of the backside opening and within the back side recesses;
forming control gates comprising a metal material over the blocking dielectric in the back side recesses through the back side opening, wherein each control gate comprises a first side surface facing the semiconductor channel in the front side opening and a second side surface opposite the first side surface that forms a portion of a sidewall of the back side opening;
oxidizing a portion of the metal material of the control gates adjacent to the second side surfaces of the control gates; and
etching the back side opening using a wet chemical etch to remove the blocking dielectric from the sidewalls and the bottom surface of the backside opening.

2. The method of claim 1 , further comprising:
forming a layer of insulating material over the sidewalls of the backside opening; and
forming an electrically conductive source line within the backside opening such that the insulating material over a sidewall of the backside opening is located between the source line and the plurality of control gates.

3. The method of claim 2 , wherein the layer of insulating material is formed over the sidewalls and bottom surface of the backside opening, the method further comprising:
removing by etching a portion of the insulating material over the bottom surface of the backside opening to expose a source region in or over the substrate, wherein the electrically conductive source line is formed in electrical contact with the source region.

4. The method of claim 1 , wherein oxidizing a portion of the metal material of the control gates comprises performing a plasma silane oxidation of the metal material through the back side opening.

5. The method of claim 4 , wherein etching the back side opening using a wet chemical etch comprises etching using a hot phosphoric acid etch.

6. The method of claim 5 , wherein the blocking dielectric comprises a metal oxide material.

7. The method of claim 6 , wherein the blocking dielectric comprises aluminum oxide.

8. The method of claim 1 , wherein the at least one memory film comprises a charge storage layer and a tunnel dielectric layer formed over the charge storage layer such that the tunnel dielectric layer is located between the charge storage layer and the semiconductor channel in the front side opening.

9. The method of claim 8 , wherein the blocking dielectric and control gates are formed within the back side recesses such that the blocking dielectric extends over the first side surface of each of the control gates and is located between each of the control gates and the charge storage layer.

10. The method of claim 1 , wherein forming the control gates comprises forming a liner layer of a metal nitride material over the blocking dielectric in each of the back side recesses and forming the metal material over the liner layer.

11. The method of claim 10 , wherein the liner layer comprises titanium nitride, the metal material comprises tungsten and oxidizing a portion of the metal material comprises forming tungsten oxide regions adjacent to the second side surfaces of the control gates.

12. The method of claim 1 , further comprising forming one of a source or drain electrode which contacts one of a source or drain region which contacts the semiconductor channel from above, and another of a source or drain electrode which contacts another one of the source or drain region which contacts the semiconductor channel below the stack to form the monolithic three dimensional NAND string in which at least one memory cell in the first device level is located over another memory cell in the second device level and the substrate comprises a silicon substrate which contains an integrated circuit comprising a driver circuit for the monolithic three dimensional NAND string located thereon.

13. The method of claim 1 , wherein:
the semiconductor channel has a U-shaped side cross section;
two wing portions of the U-shaped semiconductor channel extend substantially perpendicular to a major surface of the substrate are connected by a connecting portion which extends substantially parallel to a major surface of the substrate;
one of a source or drain electrode contacts the first wing portion of the semiconductor channel from above; and
another one of a source or drain electrode contacts the second wing portion of the semiconductor channel from above.

14. A method of making a monolithic, three dimensional NAND string, comprising:
forming a stack of alternating layers of a first material and a second material different than the first material over a substrate;
etching the stack to form a front side opening in the stack;
forming a blocking dielectric on a sidewall and a bottom surface of the front side opening;
forming a charge storage layer over the blocking dielectric on the sidewall and bottom surface of the front side opening;
forming a tunnel dielectric layer over the charge storage layer on the sidewall and bottom surface of the front side opening;
forming a semiconductor cover layer over the tunnel dielectric layer on the sidewall and bottom surface of the front side opening;
removing by a first etching process portions of the semiconductor cover layer, the tunnel dielectric layer and the charge storage layer over the bottom surface of the front side opening to expose the blocking dielectric over the bottom surface of the front side opening;
forming a protective oxide layer over the semiconductor cover layer on the sidewall of the front side opening;
removing by a second etching process the blocking dielectric over the bottom surface of the front side opening, wherein the protective oxide layer protects the semiconductor cover layer on the sidewall of the front side opening from etching damage during the second etching process, and the second etching process is different from the first etching process;
removing by a third etching process the protective oxide layer to expose the semiconductor cover layer on the sidewall of the front side opening, wherein the third etching process is different from the second etching process; and
forming a semiconductor channel over the semiconductor cover layer over the sidewall of the front side opening and contacting the bottom surface of the front side opening.

15. The method of claim 14 , wherein the first, second and third etching processes are each different from one another.

16. The method of claim 15 , wherein the first etching process comprises a reactive ion etching process and the second and third etching processes each comprise wet chemical etch processes.

17. The method of claim 14 , wherein the second etching process comprises a hot phosphoric acid etching process.

18. The method of claim 17

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Inc

Inventors

• Pachamuthu Jayavel
• Alsmeier Johann
• Matamis George
• Chien Henry

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title