Semiconductor package

Patent metadata

Field	Value
Publication number	US-11101243-B2
Application number	US-201916680657-A
Country	US
Kind code	B2
Filing date	Nov 12, 2019
Priority date	May 3, 2019
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

First claim

What is claimed is:

1. A semiconductor package comprising:
a circuit substrate including a plurality of interconnections;
a first chip on the circuit substrate;
a second chip stacked on the first chip;
a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip;
a plurality of bumps between the circuit substrate and the first chip;
a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire;
an underfill that fills a space between the circuit substrate and the first chip; and
a first dam on the circuit substrate, the first dam overlapping the first chip,
wherein the first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

2. The semiconductor package as claimed in claim 1 , wherein:
an insulating layer is between the first dam and the at least one of the plurality of interconnections such that the first dam and the at least one of the plurality of interconnections form a capacitor.

3. The semiconductor package as claimed in claim 1 , wherein the first dam is in an “I” form and overlaps one edge portion of the first chip.

4. The semiconductor package as claimed in claim 1 , wherein the first dam is between the underfill and the plurality of second pads.

5. The semiconductor package as claimed in claim 1 , wherein the first dam overlaps two edge portions of the first chip.

6. The semiconductor package as claimed in claim 5 , further comprising a plurality of third pads on an edge portion of a second side of the circuit substrate and electrically connected to the second chip through the conductive wire,
wherein the first dam is between the underfill and the plurality of second pads and between the underfill and the plurality of third pads.

7. The semiconductor package as claimed in claim 1 , further comprising:
a second dam outside the first dam, the second dam overlapping the first chip; and
a trench between the first dam and the second dam.

8. The semiconductor package as claimed in claim 7 , wherein the trench, the first dam, and the second dam extend along a same edge portion of the first chip.

9. The semiconductor package as claimed in claim 7 , wherein each of the first dam and the second dam has an “I” shape and overlaps the first chip, and the trench extends in parallel with the first dam and the second dam.

10. The semiconductor package as claimed in claim 7 , wherein the trench, the first dam, and the second dam overlap two opposite edge portions of the first chip.

11. The semiconductor package as claimed in claim 10 , wherein each of the first dam and the second dam has a “ ” shape on the circuit substrate, and the trench extends in parallel with the first dam and the second dam.

12. A semiconductor package comprising:
a circuit substrate including a plurality of interconnections;
a first chip on the circuit substrate;
a second chip stacked on the first chip;
a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip;
a plurality of bumps between the circuit substrate and the first chip;
a plurality of second pads on an edge portion of one side of the circuit substrate and electrically connected to the second chip through a conductive wire;
an underfill that fills a space between the circuit substrate and the first chip;
a first dam on the circuit substrate, the first dam overlapping the first chip and blocking a flow of the underfill; and
a second dam outside the first dam, the second dam overlapping the first chip,
wherein the second dam includes a conductive material and overlaps at least one of the plurality of interconnections.

13. The semiconductor package as claimed in claim 12 , wherein:
the second dam overlaps the at least one of the plurality of interconnections, and
an insulating layer is between the second dam and the at least one of the plurality of interconnections such that the second dam and the at least one of the plurality of interconnections form a capacitor.

14. The semiconductor package as claimed in claim 12 , wherein each of the first dam and the second dam has an “I” shape and overlaps an edge portion of the first chip.

15. The semiconductor package as claimed in claim 12 , wherein the first dam and the second dam are outside the plurality of bumps.

16. The semiconductor package as claimed in claim 12 , wherein the first dam and the second dam overlap two edge portions of the first chip.

17. The semiconductor package as claimed in claim 16 , wherein each of the first dam and the second dam has a “ ” shape on the circuit substrate.

18. A semiconductor package, comprising:
a circuit substrate;
a first chip on the circuit substrate;
a plurality of first pads disposed on the circuit substrate and arranged in a first direction;
a plurality of bumps disposed on the circuit substrate and electrically connecting the circuit substrate and the first chip;
an underfill that fills a space between the circuit substrate and the first chip; and
a first dam disposed on the circuit substrate and extending in a second direction substantially perpendicular to the first direction, at least a portion of the first dam overlapping the first chip.

19. The semiconductor package as claimed in claim 18 , further comprising:
a second dam disposed adjacent to the first dam and extending in the second direction on the circuit substrate, the second dam overlapping the first chip.

20. The semiconductor package as claimed in claim 18 , further comprising:
a second chip mounted on the first chip;
a plurality of second pads disposed on an edge portion of the circuit substrate and arranged in the second direction; and
a conductive wire connecting the plurality of second pads and the second chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jongho
• Oh Kyungsuk
• Kim Hyunki
• Lee Yongkwan
• Kim Sangsoo
• Mok Seungkon
• Oh Junyoung
• Yoo Changyoung

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W76/40 Primary

  Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title