Bonded assembly containing horizontal and vertical bonding interfaces and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11088116-B2
Application number	US-201916694438-A
Country	US
Kind code	B2
Filing date	Nov 25, 2019
Priority date	Nov 25, 2019
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.

First claim

The invention claimed is:

1. A bonded assembly comprising:
a first semiconductor die comprising first semiconductor devices, a first bonding dielectric layer, and first bonding pads having a top surface facing away from the first semiconductor devices, a bottom surface facing the first semiconductor devices and at least one sidewall between the top surface and the bottom surface; and
a second semiconductor die comprising second semiconductor devices, a second bonding dielectric layer, dielectric isolation structures vertically extending through the second bonding dielectric layer and contacting the first bonding dielectric layer, and second bonding pads having a top surface facing away from the second semiconductor devices, a bottom surface facing the second semiconductor devices and at least one sidewall between the top surface and the bottom surface;
wherein:
the sidewalls of the second bonding pads are bonded to the respective sidewalls of the first bonding pads;
the first semiconductor die further comprises a first substrate having a first major surface, and first metal interconnect structures embedded in first dielectric material layers that laterally extend along horizontal directions parallel to the first major surface, wherein the first bonding pads are electrically connected to a respective node of the first semiconductor devices through a respective subset of the first metal interconnect structures;
the second semiconductor die further comprises a second substrate having a second major surface, and second metal interconnect structures embedded in second dielectric material layers that laterally extend along the horizontal directions parallel to the second major surface, wherein the second bonding pads are electrically connected to a respective node of the second semiconductor devices through a respective subset of the second metal interconnect structures;
the first bonding pads comprise proximal bonding pads embedded within the first bonding dielectric layer and distal bonding pads having sidewalls at that least partially overlie the first bonding dielectric layer;
the proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface; and
the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface.

2. The bonded assembly of claim 1 , wherein distal horizontal surfaces of the proximal bonding pads and proximal horizontal surfaces of the distal bonding pads are located within a horizontal plane including a distal surface of the first bonding dielectric layer.

3. The bonded assembly of claim 2 , wherein the horizontal bonding interfaces between the proximal bonding pads the second bonding pads are located within the horizontal plane including the distal surface of the first bonding dielectric layer.

4. The bonded assembly of claim 2 , wherein the second bonding pads are embedded within the second bonding dielectric layer that is vertically spaced from the horizontal plane including the distal surface of the first bonding dielectric layer by a vertical spacing which is the same as a vertical thickness of the distal bonding pads.

5. The bonded assembly of claim 4 , wherein each of the vertical bonding interfaces vertically extend from the horizontal plane including the distal surface of the first bonding dielectric layer to a horizontal plane including a horizontal interface between the distal bonding pads and the second bonding dielectric layer.

6. The bonded assembly of claim 4 , wherein the dielectric isolation structures contact the first bonding dielectric layer in a horizontal plane including the distal surface of the first bonding dielectric layer.

7. The bonded assembly of claim 6 , further comprising cavities encapsulated by horizontal surfaces of the first bonding dielectric layer and the second bonding dielectric layer and by vertical surfaces of the distal bonding pads and the dielectric isolation structures.

8. The bonded assembly of claim 6 , wherein one of the second bonding pads comprises a sidewall that contacts a sidewall of one of the dielectric isolation structures.

9. The bonded assembly of claim 4 , wherein the first subset of the second bonding pads and the second subset of the second bonding pads have a same thickness and include a respective distal horizontal surface that is located within the horizontal plane including the distal surface of the first bonding dielectric layer.

10. The bonded assembly of claim 1 , wherein the dielectric isolation structures comprise silicon nitride and the first and the second bonding dielectric layers comprise silicon oxide.

11. The bonded assembly of claim 1 , wherein one of the first or the second semiconductor devices comprise three-dimensional memory devices, and the other one of the first or the second semiconductor devices comprise driver circuit devices for the three-dimensional memory devices.

Assignees

• Sandisk Technologies Llc

Inventors

• Wu Chen
• Rabkin Peter
• Higashitani Masaaki

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title