Bonded 3D integrated circuit (3DIC) structure

Patent metadata

Field	Value
Publication number	US-10319701-B2
Application number	US-201514591784-A
Country	US
Kind code	B2
Filing date	Jan 7, 2015
Priority date	Jan 7, 2015
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

First claim

What is claimed is:

1. A bonded integrated circuit (IC) structure comprising:
a first IC structure comprising a first bonding layer and a connector; and
a second IC structure bonded to the first IC structure, wherein the second IC structure comprises:
a second bonding layer over an interconnect layer, the second bonding layer bonded to and contacting the first bonding layer, wherein the connector extends past an interface between the first bonding layer and the second bonding layer; and
a contact pad in the second bonding layer, wherein the contact pad contacts a lateral surface and a sidewall of the connector, wherein the connector is electrically connected to the interconnect layer through the contact pad, wherein a bottom lateral surface of the first bonding layer extends over and is adjacent to a lateral surface of the contact pad.

2. The bonded IC structure of claim 1 , wherein the contact pad extends from the interface between the first bonding layer and the second bonding layer to an opposing surface of the second bonding layer from the first bonding layer.

3. The bonded IC structure of claim 2 , wherein a lateral surface of the contact pad is substantially level with the opposing surface of the second bonding layer.

4. The bonded IC structure of claim 1 , further comprising an air gap between the contact pad and the first bonding layer.

5. The bonded IC structure of claim 1 , wherein the connector comprises solder, copper, or a combination thereof.

6. The bonded IC structure of claim 1 , wherein the first bonding layer and the second bonding layer each comprise an oxide.

7. The bonded IC structure of claim 1 , wherein the connector is partially disposed in the first bonding layer.

8. The bonded IC structure of claim 7 , wherein a first lateral dimension of the contact pad is larger than a second lateral dimension of the connector in the first bonding layer.

9. A bonded integrated circuit (IC) structure comprising:
a first semiconductor substrate;
a first bonding layer over the first semiconductor substrate;
a contact pad in the first bonding layer, the contact pad comprising an outermost surface facing away from the first semiconductor substrate;
a second bonding layer over and contacting the first bonding layer, wherein a lateral outermost surface of the contact pad is substantially level with an interface between the second bonding layer and the first bonding layer;
a connector disposed in the first bonding layer and the second bonding layer, wherein the contact pad is disposed on a lateral surface and a sidewall of the connector, wherein a first lateral dimension of the connector within the first bonding layer is larger than a second lateral dimension of the connector within the second bonding layer; and
a second semiconductor substrate over the second bonding layer.

10. The bonded IC structure of claim 9 further comprising an air gap at an interface between the first bonding layer and the second bonding layer.

11. The bonded IC structure of claim 9 further comprising:
a plurality of first interconnect layers between the first semiconductor substrate and the first bonding layer, wherein the contact pad contacts a first conductive feature in the plurality of first interconnect layers; and
a plurality of second interconnect layers between the second semiconductor substrate and the second bonding layer, wherein the connector contacts a second conductive feature in the plurality of second interconnect layers.

12. The bonded IC structure of claim 9 , wherein the first bonding layer and the second bonding layer are dielectric layers.

13. The bonded IC structure of claim 9 further comprising one or more through vias extending the second semiconductor substrate.

14. The bonded IC structure of claim 9 , wherein a bottom lateral surface of the second bonding layer physically contacts the lateral outermost surface of the contact pad.

15. A semiconductor device comprising:
a first semiconductor substrate;
first interconnect layers over the first semiconductor substrate, wherein the first interconnect layers comprise a first conductive feature;
a first bonding layer over the first interconnect layers;
a contact pad disposed in a first opening in the first bonding layer, wherein the contact pad is confined to the first opening in the first bonding layer, wherein the contact pad comprises:
a first portion disposed along sidewalls of the first bonding layer; and
a second portion disposed on a top surface of the first conductive feature, wherein a top surface of the second portion of the contact pad is lower than a top surface of the first bonding layer;

a second bonding layer disposed over the first bonding layer; and
a connector comprising:
a first portion of the connector bonded to the first portion of the contact pad and to the second portion of the contact pad, wherein a top surface of the first portion of the connector is lower than a top surface of the first portion of the contact pad; and
a second portion of the connector protruding from the first portion and extending through the second bonding layer.

16. The semiconductor device of claim 15 further comprising:
second interconnect layers over the second bonding layer; and
a second semiconductor substrate over the second interconnect layers.

17. The semiconductor device of claim 15 further comprising a void extending between a lateral surface of the connector and the second bonding layer.

18. The semiconductor device of claim 15 , wherein the connector is wider in the first bonding layer than in the second bonding layer.

19. The semiconductor device of claim 15 , wherein a top surface of the first portion of the contact pad is substantially level with the top surface of the first bonding layer.

20. The semiconductor device of claim 15 , wherein the first portion of the contact pad has substantially a same thickness as the second portion of the contact pad.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Chiou Wen-Chih
• Liu Chung-Shi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07253

  changes in shapes · CPC title