Silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-11081556-B2
Application number	US-202016781049-A
Country	US
Kind code	B2
Filing date	Feb 4, 2020
Priority date	Feb 6, 2019
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating layer provided on a surface of the silicon carbide substrate, a gate electrode provided on the gate insulating layer, a first insulting layer provided on the gate electrode, a first layer provided on the first insulating layer, a second insulating layer provided on the first insulating layer, and an interconnect layer provided on the second insulating layer. The second insulating layer includes SiN or SiON. The first layer includes one of Ti, TiN, Ta, and TaN. The interconnect layer includes Al or Cu.

First claim

What is claimed is:

1. A silicon carbide semiconductor device comprising:
a silicon carbide substrate;
a gate insulating layer provided on a first surface of the silicon carbide substrate;
a gate electrode provided on the gate insulating layer;
a first insulting layer provided on the gate electrode;
a first layer provided on the first insulating layer;
a second layer provided on the first layer;
a third layer provided on the second layer;
a second insulating layer provided on the first insulating layer; and
an interconnect layer provided on the second insulating layer,
wherein the second insulating layer is provided on the third layer,
wherein the second insulating layer includes SiN or SiON,
wherein the first layer includes one of Ti, TiN, Ta, and TaN,
wherein the second layer includes Ni or TiAlSi,
wherein the third layer includes one of Ti, TiN, Ta, and TaN, and
wherein the interconnect layer includes Al or Cu.

2. The silicon carbide semiconductor device as claimed in claim 1 , wherein
the first layer has a thickness of 33 nm or greater and 120 nm or less, and
the third layer has a thickness of 5 nm or greater and 30 nm or less.

3. The silicon carbide semiconductor device as claimed in claim 2 , wherein
the first layer includes one of Ti, TiN, and a laminated layer of Ti and TiN,
wherein the second layer includes Ni, and
the third layer includes one of Ti, TiN, and a laminated layer of Ti and TiN.

4. The silicon carbide semiconductor device as claimed in claim 2 , further comprising:
a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

5. The silicon carbide semiconductor device as claimed in claim 2 , further comprising:
a gate trench provided on the first surface of the silicon carbide substrate,
wherein the gate insulating layer is provided on an inner wall of the gate trench, and
wherein the gate electrode is provided on the gate insulating layer at the gate trench.

6. The silicon carbide semiconductor device as claimed in claim 1 , wherein
the first layer includes one of Ti, TiN, and a laminated layer of Ti and TiN,
wherein the second layer includes Ni, and
the third layer includes one of Ti, TiN, and a laminated layer of Ti and TiN.

7. The silicon carbide semiconductor device as claimed in claim 6 , further comprising:
a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

8. The silicon carbide semiconductor device as claimed in claim 6 , further comprising:
a gate trench provided on the first surface of the silicon carbide substrate,
wherein the gate insulating layer is provided on an inner wall of the gate trench, and
wherein the gate electrode is provided on the gate insulating layer at the gate trench.

9. The silicon carbide semiconductor device as claimed in claim 1 , further comprising:
a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

10. The silicon carbide semiconductor device as claimed in claim 1 , further comprising:
a gate trench provided on the first surface of the silicon carbide substrate,
wherein the gate insulating layer is provided on an inner wall of the gate trench, and
wherein the gate electrode is provided on the gate insulating layer at the gate trench.

11. The silicon carbide semiconductor device as claimed in claim 1 , further comprising;
a drain electrode provided on a second surface of the silicon carbide substrate, opposite to the first surface provided with the gate electrode.

12. A silicon carbide semiconductor device comprising:
a silicon carbide substrate;
a gate insulating layer provided on a first surface of the silicon carbide substrate;
a gate electrode provided on the gate insulating layer;
a first insulting layer provided on the gate electrode;
a first layer provided on the first insulating layer;
a second layer provided on the first layer;
a second insulating layer provided on the first insulating layer; and
an interconnect layer provided on the second insulating layer,
wherein the second insulating layer is provided on the second layer,
wherein the first layer includes one of Ti, TiN, Ta, and TaN,
wherein the second layer includes one of Ti, TiN, Ta, and TaN,
wherein the second insulating layer includes SiN or SiON, and
wherein the interconnect layer includes Al or Cu.

13. The silicon carbide semiconductor device as claimed in claim 12 , further comprising:
a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

14. The silicon carbide semiconductor device as claimed in claim 12 , further comprising:
a gate trench provided on the first surface of the silicon carbide substrate,
wherein the gate insulating layer is provided on an inner wall of the gate trench, and
wherein the gate electrode is provided on the gate insulating layer at the gate trench.

15. A silicon carbide semiconductor device comprising:
a silicon carbide substrate;
a gate insulating layer provided on a first surface of the silicon carbide substrate;
a gate trench provided on the first surface of the silicon carbide substrate;
a gate electrode provided on the gate insulating layer;
a first insulting layer provided on the gate electrode;
a first layer provided on the first insulating layer;
a second insulating layer provided on the first insulating layer; and
an interconnect layer provided on the second insulating layer,
wherein the gate insulating layer is provided on an inner wall of the gate trench,
wherein the gate electrode is provided on the gate insulating layer at the gate trench,
wherein the first layer includes one of Ti, TiN, Ta, and TaN,
wherein the second insulating layer includes SiN or SiON, and
wherein the interconnect layer includes Al or Cu.

16. The silicon carbide semiconductor device as claimed in claim 15 , further comprising;
a drain electrode provided on a second surface of the silicon carbide substrate, opposite to the first surface provided with the gate electrode.

17. A silicon carbide semiconductor device comprising:
a silicon carbide substrate;
a gate insulating layer provided on a first surface of the silicon carbide substrate;
a gate electrode provided on the gate insulating layer;
a first insulting layer provided on the gate electrode;
a first layer provided on the first insulating layer;
a second insulating layer provided on the first insulating layer;
an interconnect layer provided on the second insulating laver; and
a drain electrode provided on a second surface of the silicon carbide substrate, opposite to the first surface provided with the gate electrode,
wherein the first layer includes one of Ti, TiN, Ta, and TaN,
wherein the second insulating layer includes SiN or SiON, and
wherein the interconnect layer includes Al or Cu.

18. The silicon carbide semiconductor device as claimed in claim 17 , further comprising:
a source electrode, including an alloy layer of Ni and Si, and provided on the first surface of the silicon carbide substrate.

19. The silicon carbide semiconductor device as claimed in claim 18 , further comprising:
a gate trench provided on the first surface of the silicon carbide substrate,
wherein the gate insulating layer is provided on an inner wall of the gate trench, and
wherein the gate electrode is provided on the gate insulating l

Assignees

• Sumitomo Electric Industries

Inventors

• Kamada Hiroyuki

Classifications

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D64/252 Primary

  for vertical or pseudo-vertical devices · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title