Silicon carbide semiconductor device having gate electrode

Patent metadata

Field	Value
Publication number	US-10014258-B2
Application number	US-201515512916-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Oct 24, 2014
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

The gate electrode is provided on the gate insulating film. The interlayer insulating film is provided to cover the gate electrode. The interlayer insulating film includes a first insulating film which is in contact with the gate electrode, contains silicon atoms, and contains neither phosphorus atoms nor boron atoms, a second insulating film which is provided on the first insulating film and contains silicon atoms and at least one of phosphorus atoms and boron atoms, and a third insulating film which contains silicon atoms and contains neither phosphorus atoms nor boron atoms. The second insulating film has a first surface which is in contact with the first insulating film, a second surface opposite to the first surface, and a third surface which connects the first surface and the second surface. The third insulating film is in contact with at least one of the second surface and the third surface.

First claim

The invention claimed is:

1. A silicon carbide semiconductor device, comprising:
a silicon carbide substrate having a main surface;
a gate insulating film provided on the main surface of the silicon carbide substrate;
a gate electrode provided on the gate insulating film; and
an interlayer insulating film provided to cover the gate electrode,
the interlayer insulating film including
a first insulating film which is in contact with the gate electrode, contains silicon atoms, and contains neither phosphorus atoms nor boron atoms,
a second insulating film which is provided on the first insulating film and contains silicon atoms and at least one of phosphorus atoms and boron atoms, and
a third insulating film which contains silicon atoms and contains neither phosphorus atoms nor boron atoms,

the second insulating film having a first surface which is in contact with the first insulating film, a second surface opposite to the first surface, and a third surface which connects the first surface and the second surface,
the third insulating film being in contact with at least one of the second surface and the third surface; wherein
the first insulating film has a fourth surface which is in contact with the gate insulating film, a fifth surface opposite to the fourth surface, and a sixth surface which connects the fourth surface and the fifth surface, and
the third insulating film is in contact with the third surface and the sixth surface.

2. The silicon carbide semiconductor device according to claim 1 , wherein the second insulating film is confined within a space formed by the first insulating film and the third insulating film.

3. The silicon carbide semiconductor device according to claim 1 , wherein the third insulating film is in contact with the second surface.

4. The silicon carbide semiconductor device according to claim 1 , wherein
the second insulating film is in contact with the main surface at the third surface, and
the third insulating film is in contact with the second surface, and is distant from the first insulating film by the second insulating film.

5. The silicon carbide semiconductor device according to claim 1 , wherein the first insulating film includes any of SiO 2 , SiN, and SiON.

6. The silicon carbide semiconductor device according to claim 1 , wherein the second insulating film includes any of PSG, BSG, and BPSG.

7. The silicon carbide semiconductor device according to claim 1 , wherein the third insulating film includes any of SiO 2 , SiN, and SiON.

8. The silicon carbide semiconductor device according to claim 1 , wherein a maximum value of a concentration of sodium atoms in the gate insulating film is less than or equal to 1×10 16 atoms/cm 3 .

9. The silicon carbide semiconductor device according to claim 1 , further comprising:
a source electrode which is in contact with the silicon carbide substrate and contains aluminum, and
a barrier layer provided between the source electrode and the interlayer insulating film.

10. The silicon carbide semiconductor device according to claim 9 , wherein the barrier layer includes TiN.

11. The silicon carbide semiconductor device according to claim 9 , wherein the source electrode includes TiAlSi.

12. The silicon carbide semiconductor device according to claim 1 , wherein the first insulating film and the second insulating film are repeatedly stacked in the interlayer insulating film.

13. A silicon carbide semiconductor device, comprising:
a silicon carbide substrate having a main surface;
a gate insulating film provided on the main surface of the silicon carbide substrate;
a gate electrode provided on the gate insulating film; and
an interlayer insulating film provided to cover the gate electrode,
the interlayer insulating film including
a first insulating film which is in contact with the gate electrode, contains silicon atoms, and contains neither phosphorus atoms nor boron atoms,
a second insulating film which is provided on the first insulating film and contains silicon atoms and at least one of phosphorus atoms and boron atoms, and
a third insulating film which contains silicon atoms and contains neither phosphorus atoms nor boron atoms,

the second insulating film having a first surface which is in contact with the first insulating film, a second surface opposite to the first surface, and a third surface which connects the first surface and the second surface,
the third insulating film being in contact with at least one of the second surface and the third surface; wherein
a maximum value of a concentration of sodium atoms in the second insulating film is higher than a maximum value of a concentration of sodium atoms in the first insulating film.

14. A silicon carbide semiconductor device, comprising:
a silicon carbide substrate having a main surface;
a gate insulating film provided on the main surface of the silicon carbide substrate;
a gate electrode provided on the gate insulating film; and
an interlayer insulating film provided to cover the gate electrode,
the interlayer insulating film including
a first insulating film which is in contact with the gate electrode, contains silicon atoms, and contains neither phosphorus atoms nor boron atoms,
a second insulating film which is provided on the first insulating film and contains silicon atoms and at least one of phosphorus atoms and boron atoms, and
a third insulating film which contains silicon atoms and contains neither phosphorus atoms nor boron atoms,

the second insulating film having a first surface which is in contact with the first insulating film, a second surface opposite to the first surface, and a third surface which connects the first surface and the second surface,
the third insulating film being in contact with at least one of the second surface and the third surface; wherein
a maximum value of a concentration of sodium atoms in the second insulating film is higher than a maximum value of a concentration of sodium atoms in the gate insulating film.

15. A silicon carbide semiconductor device, comprising:
a silicon carbide substrate having a main surface;
a gate insulating film provided on the main surface of the silicon carbide substrate;
a gate electrode provided on the gate insulating film; and
an interlayer insulating film provided to cover the gate electrode,
the interlayer insulating film including
a first insulating film which is in contact with the gate electrode, contains silicon atoms, and contains neither phosphorus atoms nor boron atoms,
a second insulating film which is provided on the first insulating film and contains silicon atoms and at least one of phosphorus atoms and boron atoms, and
a third insulating film which contains silicon atoms and contains neither phosphorus atoms nor boron atoms,

the second insulating film having a first surface which is in contact with the first insulating film, a second surface opposite to the first surface, and a third surface which connects the first surface and the second surface,
the third insulating film being in contact with at least one of the second surface and the third surface; wherein,
in a first stress test in which a gate voltage of −5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is less than or equal to 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.

Assignees

• Sumitomo Electric Industries
• Renesas Electronics Corp

Inventors

• Yamada Shunsuke
• Tanaka So
• Hamajima Daisuke
• Kimura Shinji
• Kobayashi Masayuki
• Kijima Masaki
• Hamada Maki

Classifications

• H10D12/032

  of vertical IGBTs · CPC title

• H10D64/0114 Primary

  to diamond, semiconducting diamond-like carbon or graphene · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title