Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2018358445-A1
Application number	US-201815993671-A
Country	US
Kind code	A1
Filing date	May 31, 2018
Priority date	Jun 9, 2017
Publication date	Dec 13, 2018
Grant date	—

Abstract

At a front surface of a silicon carbide base, an n − -type drift layer, a p-type base layer, a first n + -type source region, a second n + -type source region, and a trench that penetrates the first and the second n + -type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided on the gate electrode, and a barrier metal is provided on the interlayer insulating film.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor substrate of a first semiconductor type; a first semiconductor layer of the first semiconductor type provided on a front surface of the semiconductor substrate; a second semiconductor layer of a second semiconductor type provided on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer, the second side facing toward the semiconductor substrate; a first semiconductor region of the first semiconductor type selectively provided in the second semiconductor layer and having an impurity concentration that is higher than that of the semiconductor substrate; a trench penetrating the first semiconductor region and the second semiconductor layer, and reaching the first semiconductor layer; a gate insulating film provided in the trench; a gate electrode provided in the trench on the gate insulating film; an interlayer insulating film provided on the gate electrode in the trench; a barrier metal provided on the interlayer insulating film in the trench; a first electrode in contact with the first semiconductor region, the second semiconductor layer, and the barrier metal; and a second electrode provided at a rear surface of the semiconductor substrate.

2 . The semiconductor device according to claim 1 , wherein the first semiconductor region is constituted by an upper first semiconductor region and a lower first semiconductor region having respectively differing impurity concentrations determining conductivity.

3 . The semiconductor device according to claim 1 , wherein the barrier metal contains TiN or Ti.

4 . The semiconductor device according to claim 1 , wherein the interlayer insulating film has a thickness of at least 0.3 μm.

5 . The semiconductor device according to claim 1 , further comprising a second semiconductor region of the second semiconductor type selectively provided in the first semiconductor layer, the second semiconductor region being in contact with a bottom of the trench.

6 . The semiconductor device according to claim 5 , wherein the trench has a width direction and the second semiconductor region has a striped shape parallel to the width direction of the trench.

Assignees

• Fuji Electric Co Ltd

Inventors

• Kobayashi Yusuke
• Ohse Naoyuki
• Harada Shinsuke

Classifications

• H01L29/1608

  Electricity · mapped topic

• H01L29/063

  Electricity · mapped topic

• H01L29/45

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/41741 Primary

  Electricity · mapped topic