Memory arrays and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-11075219-B2
Application number	US-201916545375-A
Country	US
Kind code	B2
Filing date	Aug 20, 2019
Priority date	Aug 20, 2019
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

First claim

The invention claimed is:

1. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers; and
insulative material of the insulative tiers extending laterally across space that is laterally-between immediately-laterally-adjacent of the memory blocks in a finished operable construction of the memory array, the insulative material having elevationally-extending holes that are laterally-between and longitudinally-along the immediately-laterally-adjacent memory blocks.

2. The memory array of claim 1 wherein the holes extend through all of the alternating insulative and conductive tiers.

3. The memory array of claim 1 wherein the holes do not extend through all of the alternating insulative and conductive tiers, the holes being in an uppermost portion of the alternating insulative and conductive tiers.

4. The memory array of claim 1 wherein the holes do not extend through all of the alternating insulative tiers and conductive tiers, the holes being in a lowermost portion of the alternating insulative and conductive tiers.

5. The memory array of claim 1 wherein the holes are everywhere larger in horizontal cross-section than the channel-material strings.

6. The memory array of claim 1 wherein the holes are at least predominately filled with insulator material.

7. The memory array of claim 6 wherein the insulator material is of a composition the same as the insulative material of the insulative tiers.

8. The memory array of claim 6 wherein the insulator material is of a composition that is different from the insulative material of the insulative tiers.

9. The memory array of 1 wherein the holes are void-space.

10. The memory array of claim 1 wherein the holes are vertical or within 10° of vertical.

11. The memory array of claim 1 wherein the holes are of a circular shape in a horizontal cross-section.

12. The memory array of claim 1 comprising NAND.

13. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers; and
insulative pillars laterally-between and longitudinally-spaced along immediately-laterally-adjacent of the memory blocks in a finished operable construction of the memory array, the insulative pillars being circumferentially-surrounded by and directly against insulative material of the insulative tiers, the insulative material of the insulative tiers extending laterally across the immediately-laterally-adjacent memory blocks vertically-between immediately-vertically-adjacent of the conductive tiers, some of the insulative material that extends laterally across the immediately-laterally-adjacent memory blocks being laterally-between immediately-adjacent of the insulative pillars.

14. The memory array of claim 13 wherein the insulative pillars are of a circular shape in a horizontal cross-section.

15. The memory array of claim 13 wherein the insulative pillars are at least predominantly of a composition the same as that of the insulative tiers.

16. The memory array of claim 13 wherein the insulative pillars are at least predominantly of a composition that is different from that of the insulative tiers.

17. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, operative channel-material strings of memory cells extending through the insulative tiers and the conductive tiers; and
insulative pillars laterally-between and longitudinally-spaced along immediately-laterally-adjacent of the memory blocks in a finished operable construction of the memory array, the insulative pillars being laterally-between the immediately-laterally-adjacent memory blocks and comprising vertically-spaced and radially-projecting insulative rings that circumferentially-surround portions of individual of the insulative pillars and that project laterally into the immediately-laterally-adjacent memory blocks from there-between in the conductive tiers as compared to the insulative tiers.

18. The memory array of claim 17 wherein the rings are of a circular shape in a horizontal cross-section.

19. The memory array of claim 17 wherein the rings are at least predominantly of a composition the same as that of the insulative tiers.

20. The memory array of claim 17 wherein the rings are at least predominantly of a composition that is different from that of the insulative tiers.

Assignees

• Micron Technology Inc

Inventors

• Zhang Xiaosong
• Hu Yi
• John Tom J
• Ng Wei Yeeng
• Tiwari Chandra

Classifications

• H10P50/283

  by chemical means · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title