Semiconductor memory device including pillars

Patent metadata

Field	Value
Publication number	US-9786673-B1
Application number	US-201715407062-A
Country	US
Kind code	B1
Filing date	Jan 16, 2017
Priority date	Aug 22, 2016
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A semiconductor memory device may include: a first group of pillars having diameters which are gradually increased toward the a first side; and interlayer insulating layers and conductive patterns surrounding the pillars of the first group, the interlayer insulating layers and conductive patterns being alternately stacked.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first group of pillars having diameters which are gradually increased toward a first side; and
interlayer insulating layers and conductive patterns surrounding the pillars of the first group the interlayer insulating layers and conductive patterns being alternately stacked.

2. The semiconductor memory device according to claim 1 , further comprising:
a second group of pillars having diameters which are gradually increased toward a second side,
wherein the interlayer insulating layers and the conductive patterns also surround the pillars of the second group of pillars.

3. The semiconductor memory device according to claim 2 , further comprising an upper separation pattern interposed between the first and second group of pillars.

4. The semiconductor memory device of claim 3 , wherein the first and second sides are opposite.

5. The semiconductor memory device according to claim 2 , wherein the pillars of the first group are arranged to be symmetrical with the pillars of the second group.

6. The semiconductor memory device according to claim 3 , wherein distances between the pillars of the first group and distances between the pillars of the second group are gradually reduced toward the upper separation pattern.

7. The semiconductor memory device according to claim 3 , wherein the upper separation pattern fills a trench extending in a direction and dummy holes, the dummy holes arranged to be spaced apart from each other in the extending direction of the trench and are overlapped with the trench.

8. The semiconductor memory device according to claim 7 , wherein each of the dummy holes has a circular shape.

9. The semiconductor memory device according to claim 7 , wherein each of the dummy holes has an elliptical shape in which a length of an axis thereof in the extending direction of the trench is greater than a length of an axis thereof in a direction intersecting with the extending direction of the trench.

10. The semiconductor memory device according to claim 7 , wherein the dummy holes are spaced apart from the pillars of the first group and the pillars of the second group by distances less than distances between the pillars of the first group and distances between the pillars of the second group.

11. The semiconductor memory device according to claim 3 , wherein the conductive patterns comprises:
a first drain select line surrounding the pillars of the first group;
a second drain select line surrounding the pillars of the second group and disposed to be spaced apart from the first drain select line by the upper separation pattern; and
word lines extending to surround the pillars of the first group and the pillars of the second group, the word lines being stacked under the first drain select line and the second drain select line.

12. The semiconductor memory device according to claim 3 , wherein the diameters of the pillars of the first and second groups are gradually increased toward the upper separation pattern.

13. A semiconductor memory device comprising:
a stack including a first sidewall and a second sidewall that face each other in a first direction;
an upper separation pattern disposed between the first sidewall and the second sidewall and passing through at least portion of the stack from an upper surface of the stack;
a first row of pillars passing through the stack and disposed adjacent to the first sidewall or the second sidewall; and
an n th row of pillars (n is a natural number of 2 or more) passing through the stack and disposed adjacent to the upper separation pattern, each of the pillars of the n th row having a diameter greater than a diameter of each of the pillars of the first row.

14. The semiconductor memory device according to claim 13 , wherein the pillars of the n th row are spaced apart from each other by a distance less than a distance by which the pillars of the first row are spaced apart from each other.

15. The semiconductor memory device according to claim 13 , wherein the upper separation pattern fills a trench extending in a second direction intersecting with the first direction and dummy holes, the dummy holes spaced apart from each other in the second direction and overlapped with the trench.

16. The semiconductor memory device according to claim 15 , wherein each of the dummy holes has an elliptical shape in which a length of an axis thereof in the second direction is greater than a length of an axis thereof in the first direction.

17. The semiconductor memory device according to claim 15 , wherein the dummy holes are spaced apart from the pillars of the n th row by a distance less than a distance between the pillars of the n th row.

18. The semiconductor memory device according to claim 15 , wherein the stack includes interlayer insulating layers and conductive patterns that are alternately stacked,
wherein the conductive patterns comprises:
a first drain select line extending from the first sidewall toward the upper separation pattern;
a second drain select line disposed on a same level as a level of the first drain select line, the second drain select line extending from the second sidewall toward the upper separation pattern; and
word lines stacked below the first drain select line and the second drain select line, the word lines extending from the first sidewall toward the second sidewall.

19. The semiconductor memory device according to claim 18 , wherein the stack further comprises liner layers formed along a surface of the conductive patterns,
wherein the liner layers open toward the first sidewall and the second sidewall and extend on a sidewall of the upper separation pattern,
wherein each of the liner layers comprises a barrier metal layer.

20. A semiconductor memory device comprising:
a stack having a first sidewall and a second sidewall facing each other; and
a plurality of pillars passing through the stack,
wherein distances between the plurality of pillars are gradually reduced toward a center between the first sidewall and the second sidewall.

Assignees

• Sk Hynix Inc

Inventors

• Cho Jik Ho
• Lee Sun Chan

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11565 Primary

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic