Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials

Patent metadata

Field	Value
Publication number	US-9893083-B1
Application number	US-201615293133-A
Country	US
Kind code	B1
Filing date	Oct 13, 2016
Priority date	Oct 13, 2016
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H 3 PO 4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H 3 PO 4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

First claim

The invention claimed is:

1. A method comprising:
forming material to be etched over a substrate;
forming an etch mask comprising a silicon nitride-comprising region elevationally over the material, the etch mask comprising an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region, the elevationally-outermost portion having a greater etch rate in at least one of HF and H 3 PO 4 than does the elevationally-innermost portion;
using the etch mask as a mask while etching an elevationally-extending opening into the material; and
exposing the silicon nitride-comprising region to at least one of HF and H 3 PO 4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.

2. The method of claim 1 ,
further comprising forming elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor;
wherein the material comprises vertically-alternating tiers of different composition materials and into which the elevationally-extending opening is formed during the etching; and
further comprising:
forming channel material in the elevationally-extending opening; and
providing control gate material, control gate blocking insulator, programmable charge storage material, and tunnel insulator operably proximate the channel material; and
conducting the exposing at least before the providing of the control gate blocking insulator.

3. The method of claim 1 wherein the silicon nitride-comprising region is formed in a lowest portion of the etch mask and directly against the material.

4. The method of claim 1 wherein the etch mask is formed to comprise carbon above the silicon nitride-comprising region, and further comprising removing the carbon prior to the exposing, an elevationally-outermost surface of the silicon nitride-comprising region being exposed to the at least one of HF and H 3 PO 4 during the exposing.

5. The method of claim 1 wherein the exposing is to HF.

6. The method of claim 1 wherein the exposing is to H 3 PO 4 .

7. The method of claim 1 wherein said etch rate is constant elevationally through each of the elevationally-outermost portion and the elevationally-innermost portion.

8. The method of claim 1 wherein said etch rate is variable elevationally through each of the elevationally-outermost portion and the elevationally-innermost portion.

9. The method of claim 1 wherein difference in said etch rate is along a stepped gradient.

10. The method of claim 1 wherein difference in said etch rate is along a linear gradient.

11. The method of claim 10 wherein the linear gradient is straight.

12. The method of claim 10 wherein the linear gradient is curved.

13. The method of claim 1 wherein the elevationally-outermost portion has greater intrinsic mechanical stress in the tensile direction than does the elevationally-innermost portion.

14. The method of claim 1 wherein the elevationally-outermost portion has less carbon content, if any, than the elevationally-innermost portion.

15. The method of claim 14 wherein the elevationally-innermost portion has 0.5 to 9 atomic percent carbon.

16. The method of claim 14 wherein the elevationally-outermost portion has zero to 0.001 atomic percent carbon.

17. The method of claim 1 the elevationally-innermost portion has less boron content, if any, than the elevationally-outermost portion.

18. The method of claim 17 wherein the elevationally-outermost portion has 1 to 20 atomic percent boron.

19. The method of claim 17 wherein the elevationally-innermost portion has zero to 0.001 atomic percent boron.

20. The method of claim 1 wherein the elevationally-outermost portion is formed to comprise at least two of (a), (b), and (c), where,
(a) greater intrinsic mechanical stress in the tensile direction than the elevationally-innermost portion;
(b) less carbon content, if any, than the elevationally-innermost portion; and
(c) more boron content than in the elevationally-innermost portion, if any in the elevationally-innermost portion.

Assignees

• Micron Technology Inc

Inventors

• Wang Fei
• John Tom J
• Shrotri Kunal
• Khandekar Anish A
• Wilson Aaron R
• Hopkins John D
• Lundberg Derek F

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title