Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor

Patent metadata

Field	Value
Publication number	US-10014309-B2
Application number	US-201615231950-A
Country	US
Kind code	B2
Filing date	Aug 9, 2016
Priority date	Aug 9, 2016
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

First claim

The invention claimed is:

1. A method of forming an array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the method comprising:
forming a stack comprising vertically-alternating tiers of different composition insulating materials;
forming elevationally-extending channel openings through the alternating tiers and forming an elevationally-extending wall opening through the alternating tiers, the wall opening being laterally spaced from a row of the channel openings and extending horizontally along the row aside the channel openings;
forming programmable charge storage material and semiconductive channel material into the channel openings and into the wall opening to form an elevationally-extending pillar comprising the semiconductive channel material and the programmable charge storage material in individual of the channel openings for individual of the elevationally-extending strings and to form an elevationally-extending wall in the wall opening, the wall comprising the programmable charge storage material and the semiconductive channel material and extending horizontally along the row aside the channel openings, the wall comprising a first side facing the pillars and a second side opposite the first side facing away from the pillars, the wall not comprising any memory cell or any programmable charge storage transistor;
after forming the wall, forming access openings through the alternating tiers of different composition insulating materials on the first side of the wall;
isotropically etching one of the different composition insulating materials through the access openings that is between the tiers of the other composition insulating material and replacing the one insulating material with control gate material for the memory cells on the first side of the wall, the wall during the isotropic etching restricting lateral access of etching fluid from passing from the first side of the wall to the second side of the wall; and
providing elevationally-extending conductive vias through the alternating tiers of different composition insulating materials on the second side of the wall.

2. A method of forming an array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the method comprising:
forming a stack comprising vertically-alternating tiers of different composition insulating materials;
forming elevationally-extending channel openings through the alternating tiers and forming an elevationally-extending wall opening through the alternating tiers, the wall opening being laterally spaced from a row of the channel openings and extending horizontally along the row aside the channel openings;
forming programmable charge storage material and semiconductive channel material into the channel openings and into the wall opening to form an elevationally-extending pillar comprising the semiconductive channel material and the programmable charge storage material in individual of the channel openings for individual of the elevationally-extending strings and to form an elevationally-extending wall in the wall opening, the wall comprising the programmable charge storage material and the semiconductive channel material and extending horizontally along the row aside the channel openings, the wall comprising a first side facing the pillars and a second side opposite the first side facing away from the pillars;
after forming the wall, forming access openings through the alternating tiers of different composition insulating materials on the first side of the wall;
isotropically etching one of the different composition insulating materials through the access openings that is between the tiers of the other composition insulating material and replacing the one insulating material with control gate material for the memory cells on the first side of the wall, the wall during the isotropic etching restricting lateral access of etching fluid from passing from the first side of the wall to the second side of the wall;
providing elevationally-extending conductive vias through the alternating tiers of different composition insulating materials on the second side of the wall; and
wherein the row of channel openings contains no laterally-overlapping channel openings, and comprising forming the wall opening and the wall to extend along the row aside multiple of the channel openings in the row.

3. The method of claim 1 wherein the channel openings and the wall opening are each formed using a single masking step, the forming of the channel openings and the wall opening occurring at the same time using the same single masking step.

4. The method of claim 1 comprising forming the programmable charge storage material into the channel openings and into the wall opening at the same time.

5. The method of claim 1 comprising forming the semiconductive channel material into the channel openings and into the wall opening at the same time.

6. The method of claim 1 wherein the replacing results in individual tiers of the control gate material being directly against the wall on the first side of the wall.

7. The method of claim 1 comprising forming tunnel insulator and control gate blocking insulator into the channel openings and into the wall opening, the wall comprising the tunnel insulator and the control gate blocking insulator.

8. The method of claim 1 comprising forming the wall to comprise laterally outer linings of programmable charge storage material and semiconductive channel material and a central core comprising dielectric material.

9. The method of claim 1 wherein the providing comprises forming the conductive vias before the etching.

10. The method of claim 1 wherein the providing comprises forming the conductive vias after the etching.

11. The method of claim 1 wherein,
the wall opening is a first wall opening and the wall is a first wall; and
further comprising:
forming a second elevationally-extending wall opening into which the programmable charge storage material and the semiconductive channel material are formed to form a second wall comprising the programmable charge storage material and the semiconductive channel material, the second wall opening and second wall being angled relative to the first wall opening and the first wall.

12. The method of claim 1 wherein,
the wall opening is a first wall opening and the wall is a first wall; and
further comprising:
forming at least one additional wall opening into which the programmable charge storage material and the semiconductive channel material are formed to form at least one additional wall comprising the programmable charge storage material and the semiconductive channel material, the at least one additional wall with the first wall encircling and forming an island comprising the elevationally-extending conductive vias.

13. The method of claim 2 comprising forming the wall opening and the wall to extend along at least four channel openings in the row.

14. The method of claim 13 wherein the wall opening and the wall are formed to extend along more than four channel openings in the row.

15. The method of claim 2 comprising forming the wall opening and the wall to be parallel with the row.

16. The method of claim 2 comprising forming the wall opening and the wall to be horizontally straight-linear.

17. The method of claim 16 comprising forming the row to be horizontally straight-linear, the wall opening and the wall being formed to be parallel with the row.

Assignees

• Micron Technology Inc

Inventors

• Dorhout Justin B
• Parekh Kunal R
• Park Matthew
• Greeley Joseph Neil
• Carter Chet E
• Roberts Martin C
• Chary Indra V
• Shamanna Vinayak
• Meyer Ryan
• Tessariol Paolo

Classifications

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H10B43/10 Primary

  characterised by the top-view layout · CPC title