Memory refresh technology and computer system

Patent metadata

Field	Value
Publication number	US-11074958-B2
Application number	US-201916600034-A
Country	US
Kind code	B2
Filing date	Oct 11, 2019
Priority date	Apr 14, 2017
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

First claim

What is claimed is:

1. A memory controller, comprising:
a communications interface for configured to receiving a first plurality of access requests sent by a processor in a computer system within a first time period; and
a refresh circuit, configured to refresh a first rank in a plurality of ranks in a dynamic random access memory (DRAM) at shortened interval set to interval when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold, wherein each of the ranks comprising a plurality of DRAM cell, T is a standard average refresh interval, and N is greater than 1.

2. The memory controller according to claim 1 , wherein the communications interface is further configured to receive a second plurality of access requests within a second time period; and
the refresh circuit is further configured to:
refresh the first rank at the standard average refresh interval when a quantity of target ranks to be accessed by the second plurality of access requests is not less than the first threshold, a proportion of read requests in the second plurality of access requests is not greater than the second threshold, or a proportion of write requests in the second plurality of access requests is not greater than the specified second threshold.

3. The memory controller according to claim 1 , wherein
the communications interface is further configured to receive, while refreshing the first rank, a first access request for accessing the first rank; and
the memory controller further comprises:
a buffer, comprising a buffer queue,
wherein the memory controller being configured to buffer in the buffer queue the first access request for accessing the first rank on which a refresh operation is being performed.

4. The memory controller according to claim 3 , wherein the buffer further comprises a scheduling queue, and wherein
the communications interface is further configured to receive a second access request for accessing a second rank in the DRAM; and
the memory controller is further configured to buffer the second access request in the scheduling queue of the buffer when no refresh operation is being performed on the second rank.

5. The memory controller according to claim 1 , wherein the refresh circuit is configured to:
refresh the first rank at the shortened interval when a quantity of the first plurality of access requests is greater than a third threshold and a quantity of access requests for accessing the first rank that are in the first plurality of access requests is less than a fourth threshold, wherein the quantity of the access requests for accessing the first rank is greater than 0.

6. The memory controller according to claim 1 , wherein the refresh circuit is configured to:
refresh the first rank at the shortened interval when a quantity of access requests for accessing the first rank that are in the first plurality of access requests is not less than a fourth threshold and a quantity of postponed refreshes on the first rank is greater than a fifth threshold, wherein the fifth threshold is less than a warning value, and the warning value is configured to indicate performing a refresh operation on the first rank immediately.

Assignees

• Huawei Tech Co Ltd

Inventors

• Hu Xing
• Liang Chuanzeng
• Xiao Shihai
• Wang Kanwen

Classifications

• G11C11/40603 Primary

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C11/40618 Primary

  Refresh operations over multiple banks or interleaving · CPC title

• G06F13/1636

  using refresh · CPC title

• G06F13/1642

  with request queuing · CPC title

• G06F13/1673

  using buffers · CPC title